adc12d040civsx National Semiconductor Corporation, adc12d040civsx Datasheet

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adc12d040civsx

Manufacturer Part Number
adc12d040civsx
Description
Dual 12-bit, 40 Msps, 600 Mw A/d Converter With Internal/external Reference And Sample-and-hold
Manufacturer
National Semiconductor Corporation
Datasheet

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© 2005 National Semiconductor Corporation
ADC12D040
Dual 12-Bit, 40 MSPS, 600 mW A/D Converter with
Internal/External Reference
General Description
The ADC12D040 is a dual, low power monolithic CMOS
analog-to-digital converter capable of converting analog in-
put signals into 12-bit digital words at 40 Megasamples per
second (Msps), minimum. This converter uses a differential,
pipeline architecture with digital error correction and an on-
chip sample-and-hold circuit to minimize die size and power
consumption while providing excellent dynamic perfor-
mance. Operating on a single 5V power supply, the
ADC12D040 achieves 10.9 effective bits at 10 MHz input
and consumes just 600 mW at 40 Msps, including the refer-
ence current. The Power Down feature reduces power con-
sumption to 75 mW.
The differential inputs provide a full scale differential input
swing equal to 2V
input. Full use of the differential input is recommended for
optimum performance. The digital outputs for the two ADCs
are available on separate 12-bit buses with an output data
format choice of offset binary or 2’s complement.
For ease of interface, the digital output driver power pins of
the ADC12D040 can be connected to a separate supply
voltage in the range of 2.4V to the digital supply voltage,
making the outputs compatible with low voltage systems.
The ADC12D040’s speed, resolution and single supply op-
eration make it well suited for a variety of applications.
This device is available in the 64-lead TQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C. An evaluation board is available to facilitate the prod-
uct evaluation process
Connection Diagram
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
REF
with the possibility of a single-ended
DS200460
Features
n Binary or 2’s complement output format
n Single supply operation
n Internal sample-and-hold
n Outputs 2.4V to 5V compatible
n Power down mode
n Pin-compatible with ADC12DL066
n Internal/External Reference
Key Specifications
n SNR (f
n ENOB (f
n SFDR (f
n Data Latency
n Supply Voltage
n Power Consumption, Operating
Applications
n Ultrasound and Imaging
n Instrumentation
n Communications Receivers
n Sonar/Radar
n xDSL
n Cable Modems
— Operating
— Power Down Mode
IN
IN
IN
= 10 MHz)
= 10 MHz)
= 10 MHz)
20046001
December 2005
6 Clock Cycles
10.9 bits (typ)
600 mW (typ)
www.national.com
75 mW (typ)
68 dB (typ)
80 dB (typ)
+5V
±
5%

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adc12d040civsx Summary of contents

Page 1

... An evaluation board is available to facilitate the prod- uct evaluation process Connection Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2005 National Semiconductor Corporation Features n Binary or 2’s complement output format n Single supply operation n Internal sample-and-hold n Outputs 2 ...

Page 2

... Ordering Information Industrial (−40˚C ≤ T ADC12D040CIVS ADC12D040CIVSX ADC12D040EVAL Block Diagram www.national.com ≤ +85˚C) Package A 64 Pin TQFP 64 Pin TQFP Tape and Reel Evaluation Board 2 20046002 ...

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Pin Descriptions and Equivalent Circuits Pin No. Symbol ANALOG I A− B− REF 11 INT/EXT REF ...

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Pin Descriptions and Equivalent Circuits Pin No. Symbol 24–29 DA0–DA11 34–39 42–47 DB0–DB11 52–57 ANALOG POWER 9, 18 10, 17, 20, 61, AGND 64 DIGITAL POWER 33 32, 49 DGND ...

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Absolute Maximum Ratings (Notes Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications – Voltage ...

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Converter Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V 0V, INT/EXT = +2.0V, OEA, OEB = 0V REF ...

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DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V +3.0V 0V, INT/EXT = REF apply for ...

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AC Electrical Characteristics Note 8: To guarantee accuracy required that |V Note 9: With the test condition for V = +2.0V (4V REF Note 10: Typical figures are 25˚C, and represent most likely ...

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Specification Definitions APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conver- sion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. ...

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Timing Diagram Transfer Characteristic www.national.com Output Timing 20046010 FIGURE 1. Transfer Characteristic 10 20046009 ...

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Typical Performance Characteristics otherwise stated DNL INL & DNL vs. Supply Voltage DNL & INL vs. Clock Duty Cycle 5V 3V 20046036 DNL & INL vs. Clock Frequency 20046038 DNL ...

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Typical Performance Characteristics otherwise stated (Continued) INL & DNL vs. Temperature SNR, SINAD, SFDR vs. Clock Frequency SNR, SINAD, SFDR vs. Input Frequency www.national.com 5V 3V SNR, SINAD, SFDR vs. ...

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Typical Performance Characteristics otherwise stated (Continued) SNR, SINAD, SFDR vs. Temperature Distortion vs. Clock Frequency Distortion vs. Input Frequency 5V 3V Distortion vs. Supply Voltage 20046058 Distortion vs. Clock Duty ...

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Typical Performance Characteristics otherwise stated (Continued) Distortion vs. Temperature Power Consumption vs. Temperature IMD Response Fin = 9.6 MHz, 10.2 MHz MHz CLK www.national.com 5V 3V Power ...

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Functional Description Operating on a single +5V supply, the ADC12D040 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. The differential analog input signal is digitized to 12 bits and the reference input is buff- ...

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Applications Information Where dev is the angular difference between the two signals having a 180˚ relative phase relationship to each other (see Figure 3). Drive the analog inputs with a source impedance less than 100Ω. FIGURE 3. Angular Errors Between ...

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Applications Information FIGURE 4. Application Circuit using Transformer or Differential Op-Amp Drive Circuit FIGURE 5. Differential Drive Circuit using a fully differential amplifier. 1.3.3 Input Common Mode Voltage The input common mode voltage should value ...

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Applications Information The ADC clock line should be considered transmis- sion line and be series terminated at the source end to match the source impedance with the characteristic impedance of the clock line. It generally is not ...

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Applications Information 4.0 POWER SUPPLY CONSIDERATIONS The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 µF ceramic chip capacitor within a centimeter of each power pin. Leadless chip capacitors are preferred because they ...

Page 20

Applications Information Since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area is more important than ...

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Applications Information improve performance. The LMH6702 and the LMH6628 have been successfully used to drive the analog inputs of the ADC12D040. Also important that the signals at the two inputs have exactly the same amplitude and be exactly ...

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Physical Dimensions inches (millimeters) unless otherwise noted National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and ...

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