adc12v170hfeb National Semiconductor Corporation, adc12v170hfeb Datasheet - Page 20

• Manufacturer Part Number: adc12v170hfeb
• Description: 12-bit, 170 Msps, 1.1 Ghz Bandwidth A/d Converter With Lvds Outputs
• Manufacturer: National Semiconductor Corporation

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pin and ground should be connected to a very clean point in
the ground plane.
All analog circuitry (input amplifiers, filters, reference compo-
nents, etc.) should be placed in the analog area of the board.
All digital circuitry and dynamic I/O lines should be placed in
the digital area of the board. The ADC12V170 should be be-
tween these two areas. Furthermore, all components in the
reference circuitry and the input signal chain that are con-
nected to ground should be connected together with short
traces and enter the ground plane at a single, quiet point. All
ground connections should have a low inductance path to
ground.
7.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source
driving the CLK input must have a sharp transition region and
be free of jitter. Isolate the ADC clock from any digital circuitry
with buffers, as with the clock tree shown in Figure 5 . The
gates used in the clock tree must be capable of operating at
frequencies much higher than those used if added jitter is to
be prevented. Best performance will be obtained with a sin-
gle-ended drive input drive, compared with a differential clock.
As mentioned in Section 6.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
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from any other signals. Other signals can introduce jitter into
the clock signal, which can lead to reduced SNR perfor-
mance, and the clock can introduce noise into other lines.
Even lines with 90° crossings have capacitive coupling, so try
to avoid even these 90° crossings of the clock line.
FIGURE 5. Isolating the ADC Clock from other Circuitry
with a Clock Tree
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