adc10731 National Semiconductor Corporation, adc10731 Datasheet - Page 7

• Manufacturer Part Number: adc10731
• Description: 10-bit Plus Sign Serial I/o A/d Converters With Mux, Sample/hold And Reference
• Manufacturer: National Semiconductor Corporation

AC CHARACTERISTICS
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
C
C
Symbol
SCS
SDI
HDI
AT
AC
DSARS
HDO
AD
1H
DCS
CS(H)
CS(L)
SC
PD
PC
The following specifications apply for V
Characteristics, V
ply for T
IN
OUT
Electrical Characteristics
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifcations and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may de-
grade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to GND, unless otherwise specified.
Note 4: When the input voltage (V
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
T
, t
Jmax
0H
= 150˚C. The typical thermal resistance (
A
CS Set-Up Time, Set-Up Time from
Falling Edge of CS to Rising Edge of
Clock
DI Set-Up Time, Set-Up Time from
Data Valid on DI to Rising Edge of
Clock
DI Hold Time, Hold Time of DI Data
from Rising Edge of Clock to Data
not Valid on DI
DO Access Time from Rising Edge of
CLK When CS is “Low” during a
Conversion
DO or SARS Access Time from CS ,
Delay from Falling Edge of CS to
Data Valid on DO or SARS
Delay from Rising Edge of Clock to
Falling Edge of SARS when CS is
“Low”
DO Hold Time, Hold Time of Data on
DO after Falling Edge of Clock
DO Access Time from Clock, Delay
from Falling Edge of Clock to Valid
Data of DO
Delay from Rising Edge of CS to DO
or SARS TRI-STATE
Delay from Falling Edge of Clock to
Falling Edge of CS
CS “HIGH” Time for A/D Reset after
Reading of Conversion Result
ADC10731 Minimum CS “Low” Time
to Start a Conversion
Time from End of Conversion to CS
Going “Low”
Delay from Power-Down command to
10% of Operating Current
Delay from Power-Up Command to
Ready to Start a New Conversion
Capacitance of Logic Inputs
Capacitance of Logic Outputs
= T
J
= T
IN
− = GND for Unsigned Characteristics and f
MIN
to T
Parameter
IN
MAX
) at any pin exceeds the power supplies (V
; all other limits T
JA
+
D
) of these Paris when board mounted can be found in the following table:
= AV
= (T
(Continued)
Jmax
+
= DV
A
− T
= T
A
)/
+
J
JA
= +5.0 V
= +25˚C. (Notes 8, 9, 10)
or the number given In the Absolute Maximum Ratings, whichever is lower. For this device,
Conditions
IN
CLK
7
DC
<
, V
GND or V
= 2.5 MHz unless otherwise specified. Boldface limits ap-
REF
+ = 2.5 V
IN
>
AV
+
or DV
Jmax
DC
, V
(Note 11)
,
− 14 ns)
Typical
+
(1 t
1 CLK
1 CLK
5 CLK
), the current at that pln should be limited to 30 mA.
JA
REF
100
14
16
30
30
20
40
40
20
10
12
2
1
7
and the ambient temperature, T
CLK
− = GND, V
(Note 12)
−30 ns)
(1 t
IN
Limits
1 CLK
1 CLK
5 CLK
200
− = 2.5V for Signed
30
25
25
50
70
35
80
50
30
CLK
A
. The maximum
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cycle(min)
cycle(min)
cycle(min)
(Limits)
ns(max)
ns(max)
ns(max)
ns(max)
ns(max)
ns(min)
ns(min)
ns(min)
ns(min)
ns(min)
(max)
Units
pF
pF
µs
µs