adc1410s065 NXP Semiconductors, adc1410s065 Datasheet
adc1410s065
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adc1410s065 Summary of contents
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... ADC1410S065/080/105/125 Single 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs Rev. 02 — 4 June 2009 1. General description The ADC1410S is a single channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. ...
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... Table 1. Ordering information Type number f (Msps) Package s ADC1410S125HN/C1 125 ADC1410S105HN/C1 105 ADC1410S080HN/C1 80 ADC1410S065HN/C1 65 ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 Name Description HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads ...
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... NXP Semiconductors 5. Block diagram INP INM Fig 4. Block diagram ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 ADC1410S ERROR CORRECTION AND DIGITAL PROCESSING PGA T/H ADC CORE INPUT 14-BIT STAGE PIPELINED CLOCK INPUT STAGE AND DUTY CYCLE CONTROL Rev. 02 — 4 June 2009 Single 14-bit ADC 65, 80, 105 or 125 Msps ...
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... Pin description Table 2. Symbol REFB REFT AGND VCM VDDA AGND INM INP AGND VDDA VDDA CLKP CLKM DEC OE PWD ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 terminal 1 index area REFB REFT 30 D0 AGND 29 D1 VCM 28 D2 VDDA 27 D3 AGND ...
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... Symbol D12_D13_M 17 D12_D13_P D10_D11_M 19 D10_D11_P D8_D9_M D8_D9_P D6_D7_M D6_D7_P D4_D5_M D4_D5_P D2_D3_M D2_D3_P D0_D1_M ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 Pin description (CMOS digital outputs) [2] Pin Type Description 17 O data output bit 13 (MSB data output bit data output bit 11 20 ...
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... Thermal characteristics Table 5. Symbol R th(j-a) R th(j-c) [1] In compliance with JEDEC test board, in free air. ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 Pin description (LVDS/DDR) digital outputs) …continued [1] [2] Pin Type Description 30 O differential output data D0 and D1 multiplexed, true 31 O data valid output clock, complement ...
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... Msps; f clk CMOS mode 125 Msps; f clk LVDS DDR mode 125 Msps; f clk ADC1410S125 ADC1410S105 ADC1410S080 ADC1410S065 Power-down mode Sleep mode peak-to-peak I = <tbd> <tbd> OH 3-state; output level = 0 V 3-state; output level = V Rev. 02 — 4 June 2009 Single 14-bit ADC 65, 80, 105 or 125 Msps = 5 pF ...
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... VREF Accuracy INL integral non-linearity DNL differential non-linearity E offset error offset E gain error G Supply PSRR power supply rejection ratio ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 …continued = 1 and C DDO amb = 1 DDA DDO Conditions high impedance HIGH I = <tbd> <tbd> ...
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... MHz i IMD Intermodul MHz i ation MHz i distortion MHz 170 MHz i ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 = 1 and C DDO amb = 1 DDA DDO ADC1410S065 ADC1410S080 Min Typ Max Min - ...
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... LVDS DDR mode timing output: pins D13P, D13M to D0P, D0M, DAVP and DAVM t propagation DATA PD delay DAV [1] Measured between ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 = 1 and C DDO amb = 1 DDA DDO ADC1410S065 ADC1410S080 Min Typ Max Min Typ Max Min ...
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... SCLK LOW pulse width w(SCLKL) t set-up time su t hold time h f maximum clock frequency clk(max) ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 = 1 and C DDO amb = + amb Conditions data to SCLKH CS to SCLKH data to SCLKH CS to SCLKH Rev. 02 — 4 June 2009 Single 14-bit ADC 65, 80, 105 or 125 Msps = 5 pF ...
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... Selecting the output data standard The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface (see Table HIGH, otherwise CMOS is selected. ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 Figure 7. CS PIN control mode SCLK/DFS Data Format 2's complement SDIO/ODS LVDS DDR ...
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... LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core. 11.2.2 Anti-kickback circuitry Anti-kickback circuitry (R-C filter in injection generated by the sampling capacitance. ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 Table 21) or using pin DFS in PIN control mode (offset ) on pins INP and INM set to 0.5V I(cm) Package ESD ...
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... Analog Fig 10. Single transformer configuration suitable for baseband applications The configuration shown in both cases, the choice of transformer will be a compromise between cost and performance. ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 R R Anti-kickback circuit RC coupling versus input frequency - recommended values R 25 ...
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... The equivalent reference circuit is shown in VREF SENSE Fig 12. Single transformer configuration suitable for baseband applications If bit INTREF_EN is set to 0, the reference voltage will be determined either internally or externally as detailed in ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 ADT1-1WT ADT1-1WT 100 100 nF 100 nF REFERENCE ...
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... The gain is programmable between steps via the SPI (see Table 20). This makes it possible to improve the Spurious-Free Dynamic Range (SFDR) of the ADC1410S. The corresponding full scale input voltage range varies between 2 V (p-p) and 1 V (p-p), as shown in ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 Reference selection SPI bit SENSE pin INTREF_EN 0 AGND ...
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... Fig 17. Equivalent schematic of the common-mode reference circuit 11.3.4 Biasing The common-mode input voltage (V 0.5V DDA The graph in changes in the common-mode input voltage. ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 Reference SPI Gain Control Gain reserved ...
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... CLKM (CLKP should be connected to ground via a capacitor). LVCMOS Clock lnput Fig 19. LVCMOS Single-ended clock input Sine Clock lnput Fig 20. Sine differential clock input ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 dB SFDR (x MHz) SNR (x MHz) 0.9 V CLKP CLKM CLKP Clock lnput CLKM Rev. 02 — ...
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... When the duty cycle stabilizer is active (bit DCS_EN = 1; see between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = 0), the input clock signal should have a duty cycle of between 45 % and 55 %. ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 LVDS Clock lnput PACKAGE ESD PARASITICS ...
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... The digital output buffers can be configured as LVDS DDR by setting bit LVDS/CMOS to 1 (see Table ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 Table 19). This feature allows the user to deliver a higher Figure 23. The buffer is powered by a separate to ensure 1 3.4 V compatibility and is isolated from the ADC core. ...
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... OTR event has occurred. The OTR response can be speeded up by enabling Fast OTR (bit FASTOTR = 1; see goes HIGH four clock cycles after the OTR event. The Fast OTR detection threshold (below full scale) can be programmed via bits FASTOTR_DET. ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 VCCO 3.5 mA typ + D ...
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... ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 Table 23). Output codes Offset binary INM 00 0000 0000 0000 00 0000 0000 0000 00 0000 0000 0001 00 0000 0000 0010 00 0000 0000 0011 00 0000 0000 0100 .... 01 1111 1111 1110 ...
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... NXP Semiconductors 11.6 Timings summary 11.6.1 CMOS mode timings Fig 26. CMOS mode timing 11.6.2 LVDS DDR mode timing D D Fig 27. LDVS DDR mode timing ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 d(s) t clk CLKP CLKM 14) DATA DAV d(s) t clk ...
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... The second phase is the transfer of the data which can vary in length but will always be a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes rising edge on CS indicates the end on data transmission. ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 Instruction bytes for the SPI MSB 7 6 ...
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... Fig 29. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR Fig 30. Default mode at start-up: SCLK HIGH = 2’s complement; SDIO LOW = CMOS ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 Figure 29). Once in SPI control mode, the output data standard ...
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... Test pattern 2 R/W TESTPAT_USER 0016 Test pattern 2 R/W TESTPAT_USER 0017 Fast OTR R/W 0020 CMOS output R/W 0021 LVDS DDR O/P 1 R/W 0022 LVDS DDR O/P 2 R/W Table 18. Bit reserved OP_MODE ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 Bit 7 Bit 6 Bit 5 Bit RST - - SE_SEL DIFF/ LVDS/ CMOS ...
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... Table 19. Bit reserved Table 20. Bit reserved INTREF Table 21. Bit reserved ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 Clock control register (address 0006h)bit description Symbol Access Value SE_SEL R DIFF/SE R reserved CLKDIV R DCS_EN R Internal reference control register (address 0008h) bit description ...
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... DATA_FORMAT Table 22. Bit reserved DAVPHASE Table 23. Bit reset DIG_OFFSET ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 Output data standard control register (address 0011h) bit description Symbol Access Value R Output clock register (address 0012h) bit description Symbol ...
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... Bit TESTPAT_USER Table 26. Bit TESTPAT_USER reserved Table 27. Bit reset FASTOTR_DET ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 Test pattern register 1(address 0014h) bit description Symbol Access Value R/W 000 001 010 011 100 101 110 111 Test pattern register 2 (address 0015h) bit description ...
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... DAV_DRV DATA_DRV Table 29. Bit DAVI DATAI Table 30. Bit reserved 3 ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 CMOS output register (address 0020h) bit description Symbol Access Value R R LVDS DDR output register 1 (address 0021h) bit description ...
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... NXP Semiconductors Table 30. Bit LVDS_INTTER 11.7.4 Serial timing interface SPI timing is shown in Fig 31. SPI timing SPI timing characteristics are detailed in ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 LVDS DDR output register 2 (address 0022h) bit description Symbol Access Value Description R/W 000 001 010 011 100 ...
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... UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION IEC SOT618 Fig 32. Package outline SOT618-1 (HVQFN40) ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 1 1 2.5 scale ...
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... Release date Data sheet status 20090604 Objective data sheet • Values in Table 7 have been updated 20090528 Objective data sheet Rev. 02 — 4 June 2009 Single 14-bit ADC 65, 80, 105 or 125 Msps Change Supersedes notice - ADC1410S065_080_105_125_1 - - © NXP B.V. 2009. All rights reserved ...
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... Contact information For more information, please visit: For sales office addresses, please send an email to: ADC1410S065_080_105_125_2 Objective data sheet ADC1410S065/080/105/125 [3] Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 4 June 2009 Document identifier: ADC1410S065_080_105_125_2 ...