adc1113d125 NXP Semiconductors, adc1113d125 Datasheet
adc1113d125
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adc1113d125 Summary of contents
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... The device also includes a SPI programmable full-scale to allow flexible input voltage range from (peak-to-peak). Excellent dynamic performance is maintained from the baseband to input frequencies of 170 MHz or more, making the ADC1113D125 ideal for use in communications, imaging, and medical applications. 2. Features and benefits SNR, 66.5 dBFS ...
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... ADCB CORE 11-BIT D11 to D0 PIPELINED CLOCK INPUT STAGE & DUTY CYCLE CONTROL SCRAMBLER RESET All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface SYNCP SYNCN SWING_n SERIALIZER A CMLPA 10-bit OUTPUT CMLNA BUFFER A SERIALIZER B ...
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... All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface 42 DGND 41 DGND 40 VDDD 39 CMLPA 38 CMLNA 37 VDDD 36 DGND ADC1113D 35 DGND 34 VDDD 33 CMLNB 32 CMLPB 31 VDDD ...
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... All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface Description channel B analog input analog power supply 3 V analog power supply 3 V SPI clock data format select SPI data IO duty cycle stabilizer ...
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... Parameter thermal resistance from junction to ambient thermal resistance from junction to case All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface Description reference programming pin voltage reference input/output analog power supply 3 V Min −0.4 [1] − ...
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... SPI: pins CS, SDIO/DCS, and SCLK/DCS V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level input current IL I HIGH-level input current IH C input capacitance I ADC1113D125_2 Preliminary data sheet ADC1113D125; serial JESD204A interface Conditions Min 2.85 1. 125 Msps; - clk f =70 MHz 125 Msps; - clk MHz ...
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... LOW-level output OL voltage V HIGH-level output OH voltage Output levels 1.8 V; SWING_SEL[2:0] = 100 DDD V LOW-level output OL voltage V HIGH-level output OH voltage ADC1113D125_2 Preliminary data sheet ADC1113D125; serial JESD204A interface Conditions Min −5 track mode track mode - track mode - track mode 0.9 - peak-to-peak output 0.5 input 0.5 DC coupled ...
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... Minimum and maximum values are across the full temperature = 1 DDD amb (INAP, INBP) − 1 DDA DDD I All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface Min Typ Max - 0. 1.47 - −5 ±1.25 +5 −0.95 ± ...
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... Minimum and maximum values are across the full temperature = 1 DDD amb (INAP, INBP) − 1 DDA DDD I All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface Min Typ Max - ...
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... Minimum and maximum values are across the full temperature = 1 DDD amb (INAP, INBP) − 1 DDA DDD I All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface Min Typ Max 100 - 125 - ...
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... Preliminary data sheet = 25 °C Eye diagram receiver common-mode Eye diagram receiver common-mode All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface Figure 3 and Figure 4. Test conditions 005aaa088 005aaa089 © NXP B.V. 2010. All rights reserved. ...
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... w(SCLK) h SCLK SDIO W1 W0 R/W SPI timings All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface Min Typ °C and ...
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... NXP Semiconductors 13. Application information 13.1 Analog inputs 13.1.1 Input stage description The analog input of the ADC1113D125 supports differential or single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (V The full scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) ...
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... Figure 8 would be suitable for a baseband application. 100 nF ADT1-1WT Analog input 100 nF Single transformer configuration All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface R INAP INBP C R INAM INBM 005aaa176 100 nF 25 Ω ...
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... System reference and power management 13.2.1 Internal/external reference The ADC1113D125 has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF an SENSE (see 0 dB and −6 dB, via SPI control bits INTREF[2:0] (when bit INTREF_EN = 1; see Table 21) ...
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... All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface EXT_ref BANDGAP REFERENCE EXT_ref ADC CORE SENSE pin VREF pin GND 330 pF capacitor to GND VREF pin = SENSE pin and ...
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... Reference SPI gain control Level 0 dB −1 dB −2 dB −3 dB −4 dB −5 dB −6 dB not used All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE 005aaa117 VREF 330 pF REFERENCE EQUIVALENT ...
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... INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal performance. 13.3 Clock input 13.3.1 Drive modes The ADC1113D125 can be driven differentially (SINE, LVPECL or LVDS) with little or no influence on dynamic performances. It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to ground via a capacitor). a. Rising edge LVCMOS Fig 16 ...
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... CLKM 005aaa055 Package ESD CLKP CLKM All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface Sine clock input b. Sine clock input (with transformer) LVPECL clock input d. LVPECL clock input Figure 18. The common-mode Parasitics ...
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... If single-ended is implemented without setting SE_SEL accordingly, the unused pin should be connected to ground via a capacitor. 13.3.3 Clock input divider The ADC1113D125 contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = 1; see higher clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed ...
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... CS bits for control N' = N+CS CF: position of controls bits S samples per frame cycle HD: frame boundary break Padding with Tails bits (TT) Mx(N'xS) bits Fig 21. General overview of the JESD204A serializer ADC1113D125_2 Preliminary data sheet ADC1113D125; serial JESD204A interface VDDD 50 Ω CMLPA/CMLPB CMLNA/CMLNB − LANES FRAME ...
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... All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface LANE_MODE[1:0] 00 SCR 8-bit 10-bit 01 LANE_POLARITY ...
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... Serial Peripheral Interface (SPI) 13.6.1 Register description The ADC1113D125 serial interface is a synchronous serial communications port allowing for easy interfacing with many industry microprocessors. It provides access to the registers that control the operation of the chip in both read and write modes. This interface is configured as a 3-wire type (SDIO as bidirectional pin). ...
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... In read mode only A is active. ADC1113D125_2 Preliminary data sheet Instruction bytes All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface Register N (data) Register (data ...
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Table 17. Register allocation map [1] Addr Register name R/W Bit definition Hex Bit 7 Bit 6 ADC control registers 0003 Channel index R 0005 Reset and R/W SW_RST - Operating modes 0006 Clock R 0008 ...
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Table 17. Register allocation map …continued [1] Addr Register name R/W Bit definition Hex Bit 7 Bit 6 0821 Cfg_1_BID R/ 0822 Cfg_3_SCR_L R/W* SCR 0 0823 Cfg_4_F R/ 0824 Cfg_5_K R/ 0825 Cfg_6_M ...
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... Fully differential 1 Single-ended 0 not used select clock input divider disable 1 active duty cycle stabilizer enable: 0 disable 1 active All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface © NXP B.V. 2010. All rights reserved ...
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... Value Description 00000000 custom digital test pattern (bit All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface +31 LSB ... 0 ... −32 LSB © NXP B.V. 2010. All rights reserved ...
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... JEDEC204A unit 000 not used 0 initiates a software reset of the internal state machine of JEDEC204A unit 000 not used All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface © NXP B.V. 2010. All rights reserved ...
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... Differential mode 1 synchronization input mode is set in Single-ended mode R 1 not used All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface [2] [2] [2] [2] [2] [2] [2] © NXP B.V. 2010. All rights reserved. ...
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... Access Value Description R/W 11111111 defines the initialization vector for the scrambler polynomial (upper) All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface © NXP B.V. 2010. All rights reserved ...
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... Access Value Description R 0000000 not used R/W * defines the number of converters per device, minus 1 All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface © NXP B.V. 2010. All rights reserved ...
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... JEDEC Standard No.204A) All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface © NXP B.V. 2010. All rights reserved ...
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... PRSB generator (PRBS type is defined with “PRBS_TYPE” (Ser_PRBS_ctrl register) All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface © NXP B.V. 2010. All rights reserved ...
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... R 000 not used R/W ADC power-down control: 0 ADC is operational 1 ADC is in Power-down mode All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface © NXP B.V. 2010. All rights reserved ...
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... R 000 not used R/W ADC power-down control: 0 ADC is operational 1 ADC is in Power-down mode All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface © NXP B.V. 2010. All rights reserved ...
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... 8.1 5.95 8.1 6.55 8.0 5.80 8.0 6.40 0.5 6.5 6.5 7.9 5.65 7.9 6.25 References JEDEC JEITA - - - MO-220 All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface detail 0.5 0.4 0.1 0.05 0.05 0.1 0.3 European projection SOT684-7 c sot684-7_po Issue date ...
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... Preliminary data sheet Product status changed from Objective to Preliminary 20100412 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface Change Supersedes notice - ADC1113D125_1 - - © NXP B.V. 2010. All rights reserved. ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface © NXP B.V. 2010. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 April 2010 ADC1113D125 ADC1113D125; serial JESD204A interface © NXP B.V. 2010. All rights reserved ...
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... Register description . . . . . . . . . . . . . . . . . . . . 27 13.6.3.1 ADC control registers . . . . . . . . . . . . . . . . . . . 27 13.6.4 JESD204A digital control registers . . . . . . . . . 29 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 37 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 38 16 Legal information 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 39 ADC1113D125; serial JESD204A interface 16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 39 16.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 40 17 Contact information . . . . . . . . . . . . . . . . . . . . 40 18 Contents I(cm) Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘ ...