ad1859jrz Analog Devices, Inc., ad1859jrz Datasheet - Page 13

• Manufacturer Part Number: ad1859jrz
• Description: Stereo, Single-supply 18-bit Integrated Dac
• Manufacturer: Analog Devices, Inc.

REV. A
PCB and Ground Plane Recommendations
The AD1859 ideally should be located above a split ground
plane, with the digital pins over the digital ground plane, and
the analog pins over the analog ground plane. The split should
occur between Pins 6 and 7 and between Pins 22 and 23 as
shown in Figure 19. The ground planes should be tied together
at one spot underneath the center of the package with an ap-
proximately 3 mm trace. This ground plane strategy minimizes
RF transmission and reception as well as maximizes the AD1859’s
analog audio performance.
TIMING DIAGRAMS
The serial data port timing is shown in Figures 20 and 21. The
minimum bit clock HI pulse width is t
clock LO pulse width is t
t
left/right clock minimum hold time is t
mum setup time is t
is t
DBP
JUSTIFIED
JUSTIFIED
JUSTIFIED
DDH
. The left/right clock minimum setup time is t
SDATA
LRCLK
SDATA
SDATA
RIGHT-
MODE
MODE
MODE
BCLK
LEFT-
I
2
.
S-
Figure 19. Recommended Ground Plane
PD/RST
CMOUT
DEEMP
t
SDATA
LRCLK
DDS
IDPM0
IDPM1
AGND
MUTE
EMPL
OUTL
BCLK
t
18/16
DBH
t
Figure 20. Serial Data Port Timing
DDH
NC
t
DLS
t
10
11
12
13
14
MSB
DDS
1
2
3
4
5
6
7
8
9
DDS
t
t
DBP
DBL
GROUND PLANE
GROUND PLANE
, and the minimum serial data hold time
MSB-1
MSB
DBL
t
DDH
ANALOG
DIGITAL
. The minimum bit clock period is
t
DDS
MSB
DBH
DLH
t
DDH
, and the minimum bit
. The serial data mini-
19
18
17
16
15
28
27
26
25
24
23
22
21
20
FILT
FGND
EMPR
OUTR
NC
AV
NC
CLATCH
CDATA
CCLK
DGND
DV
XTALO
XTALI/MCLK
DD
DD
DLS
t
DDS
LSB
, and the
t
DDH
–13–
The serial control port timing is shown in Figure 22. The mini-
mum control clock HI pulse width is t
control clock LO pulse width is t
clock period is t
t
minimum control latch delay is t
LO pulse width is t
width is t
The master clock (or crystal input) and power down/reset tim-
ing is shown in Figure 23. The minimum MCLK period is t
which determines the maximum MCLK frequency at F
minimum MCLK HI and LO pulse widths are t
respectively. The minimum reset LO pulse width is t
XTALI/MCLK periods) to accomplish a successful AD1859 re-
set operation.
CSU
XTALI/MCLK
LEFT-JUSTIFIED
Figure 21. Serial Data Input Port Timing DSP Serial
Port Style
, and the minimum control data hold time is t
PD/RST
CLATCH
Figure 23. MCLK and Power Down/Reset Timing
PORT STYLE
DSP SERIAL
CDATA
CCLK
CLH
LRCLK
SDATA
MODE
BCLK
Figure 22. Serial Control Port Timing
.
t
MCH
CCP
t
CCH
. The control data minimum setup time is
CLL
t
t
, and the minimum control latch HI pulse
t
CCL
DLS
CSU
t
MCL
t
t
DBH
CHD
t
CCP
t
PDRP
t
DLH
CLD
CCL
LSB
t
MCP
, the minimum control latch
. The minimum control
CCH
t
CLD
MSB
t
CLL
, and the minimum
t
DDH
t
DDS
t
DBP
AD1859
MCH
t
CLH
CHD
MSB-1
and t
PDRP
. The
t
DBL
MC
(four
MCL
. The
MCP
,
,