tda8044h NXP Semiconductors, tda8044h Datasheet - Page 2

• Manufacturer Part Number: tda8044h
• Description: Satellite Demodulator And Decoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FEATURES
2000 Feb 21
General features:
– One-chip Digital Video Broadcasting (DVB)
– 3.3 V supply voltage (input pads are 5 V tolerant)
– Standby mode for low power dissipation
– Internal clock PLL to allow low frequency crystal
– Power-on reset module
– Package: QFP100
– Boundary scan test.
QPSK/BPSK demodulator:
– Interpolator and anti-alias filter to handle a large
– On-chip AGC of the analog input I and Q baseband
– Two on-chip matched Analog-to-Digital Converters
– Half Nyquist (square root raised-cosine) filter with
– Large range of symbol frequencies:
– Can be used at low channel Signal-to-Noise ratio
– Internal carrier recovery, clock recovery and AGC
– Two loop carrier recovery enabling phase tracking of
– Software carrier sweep for low symbol rate
– Signal-to-noise ratio estimation
– External indication of demodulator lock.
Viterbi decoder:
– Rate
– Constraint length K = 7 with G
– 4 bits input for ‘soft decision’ for both I and Q
Satellite demodulator and decoder
compliant Quadrature Phase Shift Keying (QPSK)
and Binary Phase Shift Keying (BPSK) demodulator
and concatenated Viterbi/Reed-Solomon decoder
with de-interleaver and de-randomizer
(ETS 300 421)
application and selectable clock frequencies
range of symbol rates without additional external
filtering
signals or tuner AGC control
(ADCs; 7 bits)
selectable roll-off factor
0.5 to 45 Msymbols/s for TDA8044 and
0.5 to 30 Msymbols/s for TDA8044A, including
Single Carrier Per Channel (SCPC) function
(S/N)
loops with programmable loop filters
the incoming symbols
applications
G
1
2
2
,
= 133
2
3
1
,
2
3
convolutional code based
4
oct
,
4
; supported puncturing code rates:
5
,
5
6
,
6
7
,
7
8
and
8
9
1
= 171
oct
and
2
APPLICATIONS
– Truncation length: 144
– Automatic synchronization
– Channel Bit Error Rate (BER) estimation
– External indication of Viterbi sync lock
– Differential decoding optional.
Reed-Solomon (RS) decoder:
– (204, 188, T = 8) Reed-Solomon code
– Automatic (I
– Internal convolutional de-interleaving (I = 12; using
– De-randomizer based on Pseudo Random Bit
– External indication of Register Select (RS) decoder
– External indication of uncorrectable error (transport
– External indication of corrected byte
– Indication of the number of lost blocks
– Indication of the number of corrected blocks.
Interface:
– I
– Programmable interrupt facility
– 6 bits I/O expander for flexible access to and from the
– Switchable I
– DiSEqC level 1.X support for dish control applications
– 3-state mode for transport stream outputs.
Digital satellite TV: demodulation and Forward Error
Correction (FEC).
bytes, transport packets and frames
internal memory)
Sequence (PRBS)
sync lock
error indicator is set)
demodulator and Forward Error Correction (FEC)
decoder; when no I
defined
I
crosstalk in the tuner
2
2
C-bus interface to initialize and monitor the
C-bus
2
2
C-bus configurable) synchronization of
C-bus loop-through to suppress I
2
C-bus usage, default mode is
Product specification
TDA8044
2
C-bus