pca9540dp NXP Semiconductors, pca9540dp Datasheet - Page 10

• Manufacturer Part Number: pca9540dp
• Description: 2-channel I2c Multiplexer
• Manufacturer: NXP Semiconductors

Philips Semiconductors
AC CHARACTERISTICS
NOTES:
1. Pass gate propagation delay is calculated from the 20 Ω typical R
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH
3. C
2003 Dec 18
SYMBOL
SYMBOL
t
t
t
2-channel I
t
t
t
t
t
VD:DATH
VD:DATL
SU;STO
HD;DAT
VD:ACK
HD;STA
SU;STA
SU;DAT
the undefined region of the falling edge of SCL.
t
t
f
t
HIGH
LOW
BUF
t
t
SCL
C
b
t
t
SP
pd
R
F
b
= total capacitance of one bus line in pF.
SDA
SCL
Propagation delay from SDA to SD
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition
After this period, the first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Set-up time for STOP condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Capacitive load for each bus line
Pulse width of spikes which must be suppressed
by the input filter
Data valid (HL)
Data valid (LH)
Data valid Acknowledge
P
t
BUF
2
C multiplexer
S
t
HD;STA
PARAMETER
PARAMETER
t
LOW
t
t
Figure 13. Definition of timing on the I
R
HD;DAT
n
or SCL to SC
t
HIGH
n
ON
t
F
10
and and the 15 pF load capacitance.
t
SU;DAT
STANDARD-MODE
MIN
250
4.7
4.0
4.7
4.0
4.7
4.0
—
0
—
—
—
—
—
—
—
0
2
I
2
C-BUS
2
C-bus
Sr
MAX
1000
3.45
0.3
100
300
400
0.6
50
—
—
—
—
—
—
—
1
1
1
t
SU;STA
t
HD;STA
20 + 0.1C
20 + 0.1C
min
MIN
100
1.3
0.6
1.3
0.6
0.6
0.6
—
0
—
—
—
—
—
of the SCL signal) in order to bridge
FAST-MODE
0
2
I
2
C-BUS
b
b
3
3
t
SP
t
SU;STO
MAX
0.3
400
300
300
400
0.9
0.6
50
—
—
—
—
—
—
—
1
1
1
PCA9540
SU00645
P
Product data
UNIT
UNIT
kHz
ns
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
ns
µs
µs
µs