pca9557bs NXP Semiconductors, pca9557bs Datasheet - Page 7

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pca9557bs

Manufacturer Part Number
pca9557bs
Description
8-bit I2c And Smbus I/0 Port With Reset
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
7. Functional description
PCA9557_5
Product data sheet
7.1 Device address
7.2 Control register
Refer to
Following a START condition the bus master must output the address of the slave it is
accessing. The address of the PCA9557 is shown in
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9557, which will be stored in the control register. This register can be
written and read via the I
Table 4.
D1
0
0
1
1
Fig 8. PCA9557 device address
Fig 9. Control register
Figure 1 “Block diagram of
D0
0
1
0
1
Register definition
Name
Register 0
Register 1
Register 2
Register 3
Rev. 05 — 12 September 2007
2
C-bus.
bit:
0
7
0
0
fixed
PCA9557”.
6
0
Access
read-only
read/write
read/write
read/write
slave address
1
5
0
1
8-bit I
4
0
programmable
A2
3
0
2
A1
C-bus and SMBus I/O port with reset
2
0
Figure
A0 R/W
002aad279
Description
Input port register
Output port register
Polarity inversion register
Configuration register
D1
002aad280
1
D0
0
8. To conserve power, no
PCA9557
© NXP B.V. 2007. All rights reserved.
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