pca9558pw NXP Semiconductors, pca9558pw Datasheet - Page 9

• Manufacturer Part Number: pca9558pw
• Description: 8-bit I2c And Smbus I/o Port With 5-bit Multiplexed/1-bit Latched 6-bit I2c Eeprom And 2 K Bit Eeprom
• Manufacturer: NXP Semiconductors

Philips Semiconductors
EEPROM write operation
6-bit write operation
A write operation to the 6-bit EEPROM requires that an address
byte be written after the command byte. This address points to the
6-bit address space in the EEPROM array. Upon receipt of this
address, the PCA9558 waits for the next byte that will be written to
the EEPROM. The master then ends the transaction with a STOP
condition on the I
After the STOP condition, the E/W cycle starts, and the parts will not
respond to any request to access the EEPROM array until the cycle
finishes, approximately 4 ms.
6-bit read operation
A read operation is initiated in the same manner as a write
operation, with the exception that after the word address has been
written a REPEATED START condition is placed on the I
the direction of communication is reversed (see Figure 13).
256 byte write operation (I
A write operation to the 256 byte EEPROM requires that an address
byte be written after the command byte. This address points to the
starting address in the EEPROM array. The four LSBs of this
address select a position on a 16 byte page register, the 4 MSBs
select which page register. The four LSBs will be auto-incremented
after receipt of each byte of data; in this manner, the entire page
register can be written starting at any point. Up to 16 bytes of data
may be sent to the PCA9558, followed by a STOP condition on the
I
generating a STOP condition, data within the address page will be
overwritten and unpredictable results may occur. See Figure 14.
After the STOP condition, the E/W cycle starts, and the parts will not
respond to any request to access the EEPROM array until the cycle
finishes, approximately 4 ms.
2003 Jun 27
2
C-bus. If the master sends more than 16 bytes of data prior to
8-bit I
latched 6-bit I
S
1
SLAVE ADDRESS
0
0
2
S
C and SMBus I/O port with 5-bit multiplexed/1-bit
1
1
2
SLAVE ADDRESS
1
C. See Figure 12.
0
1 A0 0
0
ACKNOWLEDGE
FROM SLAVE
1
R/W
2
2
1
C EEPROM DIP switch and 2-kbit EEPROM
C)
A
1 A0 0
0
ACKNOWLEDGE
0
FROM SLAVE
COMMAND BYTE
R/W
0
A
0
0
0
0
1
COMMAND BYTE
ACKNOWLEDGE
FROM SLAVE
1
0
Figure 12. I
Figure 13. I
0
0
A
0
2
C-bus and
1
1
EEPROM ADDRESS
1
0
ACKNOWLEDGE
FROM SLAVE
1
2
0
2
C write of 6-bit EEPROM
C read of 6-bit EEPROM
1
A
1
1
9
1
ACKNOWLEDGE
1
EEPROM ADDRESS
FROM SLAVE
256 byte read operation (I
A read operation is initiated in the same manner as a write
operation, with the exception that after the word address has been
written, a REPEATED START condition is placed on the I
and the direction of communication is reversed. For a read
operation, the entire address is incremented after the transmission
of each byte, meaning that the entire 256 byte EEPROM array can
be read at one time. See Figure 15.
256 byte EEPROM write to GPIO
A mode is available whereby a byte of data in the 256 byte
EEPROM array can be written to the GPIO (OPR). This is initiated
by the I
the 256 byte EEPROM and write to the GPIO is sent, followed by
the word address of the data within the EEPROM array. Upon
ACKNOWLEDGE from the slave, the data is sent to the GPIO. See
Figure 16.
256 byte EEPROM write from GPIO
A mode is available whereby data in the GPIO (IPR) can be written
to the 256 byte EEPROM. This is initiated by the I
mode, a control word indicating a read from the GPIO and write to
the 256 byte EEPROM is sent, followed by the word address for the
data to be written. Once the slave sent an ACKNOWLEDGE, the
master must send a STOP condition. See Figure 17.
After the STOP condition, the E/W cycle starts, and the parts will not
respond to any request to access the EEPROM array until the cycle
finishes, approximately 4 ms.
When the Write Protect (WP) input is a logic 0 it allows writes to
both EEPROM arrays. When a logic 1, it prevents any writes to the
EEPROM arrays.
1
1
1 A
1
2
1
S
C-bus. In this mode, a control word indicating a read from
1
1
0
ACKNOWLEDGE
1
FROM SLAVE
SLAVE ADDRESS
0
1 A
1
1
X
ACKNOWLEDGE
1 A0
DATA FOR 6bitEEPROM
X
FROM SLAVE
2
C)
d5 d4 d3 d2 d1 d0 A
R/W
1
A
PROGRAMMING BEGINS AFTER STOP
0
DATA FROM 6bitEEPROM
0 d5 d4 d3 d2 d1 d0 NA P
ACKNOWLEDGE
FROM SLAVE
SW00640
PCA9558
2
NO ACKNOWLEDGE
P
C-bus. In this
FROM MASTER
SW00641
Product data
2
C-bus,