pca9504a NXP Semiconductors, pca9504a Datasheet - Page 3

• Manufacturer Part Number: pca9504a
• Description: Glue Chip 4
• Manufacturer: NXP Semiconductors

Philips Semiconductors
PIN DESCRIPTION
2004 May 11
1
2
3
4
5
6
7
8
9
10
11, 29, 43
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
30
31
32
33
34
35
36
37
38
39
40
41
42
44
45
46
47
48
49
Glue chip 4
PIN(S)
3I
P
P
3IU
REF
REF
5V OD
5V OD
3I
3IU
G
3I
3O
3IU
3O
5O
3IOD
5IOD
3IOD
5IOD
3IU
3I
5V OD
5V OD
5IU
5IU
5IU
5V OD
5O
5V OD
5IU
5IU
3O
5V OD
3I
3IU
3IU
5V OD
5V OD
5ID
3O
AO
5I
3IU
5O
AO
3I
VREF3IN
V_5P0_STBY
V_3P3_STBY
GPO_FLUSH_CACHE / GP2_IN
A20M / GP1_INB
INIT / GP1_INA
FLUSH_OUT_CPU / GP1_OUT
INIT_OUT / GP2_OUT
CLK_IN
SEL_33_66
GND
PCRIST
PCRIST_OUT
AUD_EN
AUD_RST
IDE_RSTDRV
3V_DDCSCL
5V_DDCSCL
3V_DDCSDA
5V_DDCSDA
CPU_PRESENT
SLP_S3
PS_ON
HD_LED
PRIMARY_HD
SCSI
SECONDARY_HD
BACKFEED_CUT
LATCHED_BACKFEED_CUT
FLUSH_OUT_FWH
PWRGD_PS
FPRST
PWRGD_3V
SCK_BJT_GATE
SLP_S5
GRN_BLNK
YLW_BLNK
YLW_LED
GRN_LED
TEST_EN
RSMRST
REF5V
VREF5IN
MUTE_AUD
AUD_SHDN
REF5V_STBY
HSYNC_3V
SYMBOL
3
3.3 V input
5 V system standby power supply
3 V system standby power supply
GPO from SIO / ICH2 / Buffer 2 input
A20M signal from ICH2 / NAND 1 input B
INIT signal from the ICH2 / Buffer 1 input A
Open drain signal, goes to the CPU / NAND 1 output
Delayed INIT signal into the CPU / Buffer 2 output
Either 33MHz or 66MHz clock, based on SEL_33_66 pin
Strapping option for 33MHz or 66MHz CLK_IN
Ground
PCI reset signal
Copy of PCRIST, increased drive-strength
Audio enable input (GPO from ICH2 / SIO)
Audio reset output
IDE reset output, 5 V push/pull
DDCSCL input/output 3.3 V side
DDCSCL input/output 5 V side
DDCSDA input/output 3.3 V side
DDCSDA input/output 5 V side
CPU present signal from the processor
Signal from ICH2 for transitioning to the S3 power state
Power supply turn-on signal
Hard drive front panel LED output
IDE primary drive active input
SCSI drive active input
IDE secondary drive active input
Signal used for STR circuitry
Signal used for STR circuitry
Open drain signal, goes to the FWH
Power good signal from power supply
Reset signal from the front panel
3.3 V power good output
Gate signal from the SCK BJT in suspend to RAM
Signal from the ICH2 for transitioning to the S5 power state
Power LED input, from SIO GPIO
Power LED input, from SIO GPIO
Power LED output
Power LED output
Test enable, 100K internal pull-down to GND
Reset for the ICH2 resume well
Highest system supply reference voltage
5V system primary supply input
Signal from SIO to mute audio on power up/down
Signal to audio amp to signal shutdown
Highest system standby voltage
HSYNCH input from chipset video
FUNCTION
PCA9504A
Product data