adv7173 Analog Devices, Inc., adv7173 Datasheet - Page 16

• Manufacturer Part Number: adv7173
• Description: With Six Dacs 10 Bits , Color Control And Enhanced Power Management
• Manufacturer: Analog Devices, Inc.

ADV7172/ADV7173
Mode 0 (CCIR–656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7172/ADV7173 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel Data.
All timing information is transmitted using a 4-byte Synchronization Pattern. A synchronization pattern is sent immediately before
and after each line during active picture and retrace. Mode 0 is illustrated in Figure 23. The HSYNC, FIELD/VSYNC, and BLANK
(if not used) pins should be tied high during this mode.
RTC
NOTES
1
2
3
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
F
OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE
ADV7172/ADV7173.
SEQUENCE BIT
RESET BIT
RESET ADV7172/ADV7173’s DDS
SC
PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7172/ADV7173 FSC DDS REGISTER IS F
NTSC/PAL M SYSTEM
(525 LlNES/60Hz)
(625 LINES/50Hz)
H/LTRANSITION
COUNT START
INPUT PIXELS
PAL SYSTEM
TIME SLOT: 01
128
ANALOG
VIDEO
COMPOSITE
OR CABLE
LOW
e.g., VCR
VIDEO
13
ADV7172/ADV7173
RESERVED
Y
END OF ACTIVE
14 BITS
NOT USED IN
VIDEO LINE
C
r Y
F
F
4 CLOCK
4 CLOCK
EAV CODE
DECODER
ADV7185
0
0
VIDEO
P19-P12
LCC1
14
0
0
0
RESERVED
X
Y
GLL
4 BITS
8
0
19
21
1
0
8
0
1
0
ANCILLARY DATA
0
0
SCRESET/RTC
CLOCK
HSYNC
FIELD/VSYNC
268 CLOCK
280 CLOCK
P7–P0
F
F
(HANC)
F
F
SAMPLE
FSCPLL INCREMENT
ADV7172/ADV7173
VALID
A
B
A
B
A
B
GREEN/COMPOSITE/Y
GREEN/COMPOSITE/Y
INVALID
SAMPLE
8
0
RED/CHROMA/V
RED/CHROMA/V
1
0
BLUE/LUMA/U
BLUE/LUMA/U
8
0
1
1
0
SC
SAV CODE
F
F
4 CLOCK
4 CLOCK
PLL INCREMENT BITS 21:0 PLUS BITS 0:9
START OF ACTIVE
0
0
VIDEO LINE
0
0
X
Y
C
b
8/LLC
Y C
RESERVED
1440 CLOCK
1440 CLOCK
r
5 BITS
Y
SEQUENCE
0
C
b
BIT
Y
2
C
r
67 68
Y
RESET
BIT
C
b
3
RESERVED