adv7314 Analog Devices, Inc., adv7314 Datasheet
adv7314
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adv7314 Summary of contents
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... It includes six high speed NSV video D/A converters with TTL compatible inputs. The ADV7314 has separate 8-/10-/16-/20-bit input ports that accept data in high definition and/or standard definition video format. For all standards, external horizontal, vertical and ...
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... ADV7314 DETAILED FEATURES High Definition Programmable Features (720p/1080i) 2 Oversampling (148.5 MHz) Internal Test Pattern Generator (Color Hatch, Black Bar, Flat Field/Frame) Fully Programmable YCrCb to RGB Matrix Gamma Correction Programmable Adaptive Filter Control Programmable Sharpness Filter Control CGMS-A (720p/1080i) Programmable Features (525p/625p) ...
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... Mode 0 (CCIR-656)—Master Option . . . . . . . . . . . . . . . 67 Mode 1—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Mode 1—Master Option . . . . . . . . . . . . . . . . . . . . . . . . . 69 Mode 2—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Mode 2—Master Option . . . . . . . . . . . . . . . . . . . . . . . . . 71 Mode 3—Master/Slave Option . . . . . . . . . . . . . . . . . . . . . 72 APPENDIX 6—HD TIMING . . . . . . . . . . . . . . . . . . . . . . 73 APPENDIX 7—VIDEO OUTPUT LEVELS . . . . . . . . . . . 74 HD YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . . 74 RGB Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 APPENDIX 8—VIDEO STANDARDS . . . . . . . . . . . . . . . 80 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 82 –3– ADV7314 ...
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... ADV7314–SPECIFICATIONS Parameter 1 STATIC PERFORMANCE Resolution Integral Nonlinearity 2 Differential Nonlinearity , +ve 2 Differential Nonlinearity , –ve DIGITAL OUTPUTS Output Low Voltage Output High Voltage Three-State Leakage Current Three-State Output Capacitance DIGITAL AND CONTROL INPUTS Input High Voltage Input Low Voltage, V ...
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... Typ Max 12.5 5.8 65 13.75 0.44 0.20 0.84 –0.2 0 97.5 0 0.1 84 75.3 0.09 0.12 63.5 77.7 –5– ADV7314 = 2.375 V–3 1.235 V, R DD_IO REF C), unless otherwise noted.) MIN MAX Unit Test Conditions MHz MHz dB Luma Ramp Unweighted dB Flat Field Full Bandwidth MHz MHz H % ± % Referenced to 40 IRE ± ...
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... ADV7314 TIMING SPECIFICATIONS Parameter 1 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, SCLOCK Rise Time SDATA, SCLOCK Fall Time Setup Time (Stop Condition), t ...
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... Figure 2. HD Only 4:4:4 Input Mode [Input Mode 010]; PS Only 4:4:4 Input Mode [Input Mode 001] REV Cb0 Cr0 Cb2 Cr2 Cb4 Cb0 Cb1 Cb2 Cb3 Cb4 t 11 Cr0 Cr1 Cr2 Cr3 Cr4 –7– ADV7314 Y4 Y5 Cr4 Cb5 t 13 Cr5 t 14 ...
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... ADV7314 CLKIN_A P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 C9–C0 S9–S0 CONTROL OUTPUTS t = CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP TIME DATA HOLD TIME 12 Figure 3. HD RGB 4:4:4 Input Mode [Input Mode 010] CLKIN_B* P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK ...
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... *CLKIN_B USED IN THIS PS ONLY MODE 3FF NOTE: Y0, Cb0 SEQUENCE AS PER SUBADDRESS 0x01 BIT 1 –9– ADV7314 Crxxx Yxxx Cb0 Y0 Cr0 Cb0 Y0 Cr0 Y1 ...
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... ADV7314 CLKIN_B P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 Y0 C9–C0 Cb0 CLKIN_A t S_HSYNC, CONTROL S_VSYNC, INPUTS S_BLANK S9–S0 Cb0 Figure 8. HD 4:2:2 and SD (10-Bit) Simultaneous Input Mode [Input Mode 101]; SD Oversampled [Input Mode 110] HD Oversampled CLKIN_B t P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 Y0 C9– ...
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... Figure 11. 10-/8-Bit SD Only Pixel Input Mode [Input Mode 000] REV Cr0 Y1 Crxxx Cr0 Cb1 Cr0 Cb2 Cr2 Cb4 –11– ADV7314 PS INPUT Yxxx SD INPUT Y2 IN SLAVE MODE Cr4 IN MASTER/SLAVE MODE ...
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... ADV7314 CLKIN_A t 9 S_HSYNC, CONTROL S_VSYNC, INPUTS S_BLANK S9–S0/Y9–Y0* Y0 C9–C0 Cb0 CONTROL OUTPUTS *SELECTED BY ADDRESS 0x01 BIT 7 Figure 12. 20-/16-Bit SD Only Pixel Input Mode [Input Mode 000] P_HSYNC P_VSYNC P_BLANK Y9–Y0 C9– CLK CYCLES FOR 525p CLK CYCLES FOR 626p ...
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... BY ADDRESS 0x01 BIT 7 SDA SCLK REV Figure 15. SD Timing Input for Timing Mode Figure 16. MPU Port Timing Diagram –13– ADV7314 PAL = 24 CLK CYCLES NTSC = 32 CLK CYCLES ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7314 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode and HD. Video Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode and HD. Video Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD. Video Blanking Control Signal for SD only. –15– ADV7314 S_BLANK 47 ...
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... SD or Progressive Scan/HDTV Input Port for Cr [Red/V] Data in 4:4:4 Input Mode. LSB is set up on Pin S0. For 8-bit data input, LSB is set up on S2. This input resets the on-chip timing generator and sets the ADV7314 into default register setting. RESET is an active low signal. ...
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... Figure 17. The LSB sets either a read or write operation. Logic 1 corresponds to a read operation, while Logic 0 corresponds to a write opera- tion set by setting the ALSB pin of the ADV7314 to Logic 0 or Logic 1. When ALSB is set to 1, there is greater 2 ...
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... ADV7314 Before writing to the subcarrier frequency registers, the ADV7314 must have been reset at least once since power-up. The four subcarrier frequency registers must be updated start- ing with subcarrier frequency register 0 through subcarrier frequency register 3. The subcarrier frequency will not update until the last subcarrier frequency register byte has been received by the ADV7314 ...
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... ADV7314 Register Reset Register Setting Value (Shaded) 0 Sleep Mode off FCh 1 Sleep Mode on 0 PLL on 1 PLL off 0 DAC F off 1 DAC F on DAC E off DAC E on DAC D off DAC D on ...
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... ADV7314 SR7- SR0 Register Bit Description 02h Mode Register 0 Reserved Test Pattern Black Bar RGB Matrix 1 Sync on RGB RGB/YUV Output SD Sync HD Sync 03h RGB Matrix 0 04h RGB Matrix 1 05h RGB Matrix 2 06h RGB Matrix 3 07h RGB Matrix 4 08h RGB Matrix 5 09h ...
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... ADV7314 Register Setting Reset Values 0 EIA770.2 output 00h 1 EIA770.1 output 0 Output levels for full input range 1 Reserved HSYNC, VSYNC, BLANK EAV/SAV codes Async timing mode Reserved 525p 625p 1080i 720p ...
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... ADV7314 SR7- SR0 Register Bit Description Bit 7 12h HD Mode HD Y Delay with Register 3 Respect to Falling Edge of HSYNC HD with Respect to Falling Edge of HSYNC HD CGMS HD CGMS CRC 0 1 13h HD Mode HD Cr/Cb Sequence Register 4 Reserved HD Input Format Sinc Filter on DAC Reserved HD Chroma SSAF HD Chroma Input ...
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... ADV7314 Register Setting Reset Value x Y color value A0h x Cr color value color value Disabled Enabled ...
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... ADV7314 SR7–SR0 Register Bit Description 38h HD Adaptive Filter HD Adaptive Filter Gain 1 Value A Gain 1 HD Adaptive Filter Gain 1 Value B 39h HD Adaptive Filter HD Adaptive Filter Gain 2 Gain 2 Value A HD Adaptive Filter Gain 2 Value B 3Ah HD Adaptive Filter HD Adaptive Filter Gain 3 Gain 3 Value A HD Adaptive Filter ...
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... ADV7314 Register Setting Reset Bit 0 Value 00h 00h 0 00h NTSC 1 PAL PAL M 1 PAL N LPF NTSC LPF PAL Notch NTSC Notch PAL SSAF Luma Luma CIF ...
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... ADV7314 SR7– SR0 Register Bit Description Mode Register SD VSYNC–3H SD RTC/TR/SCR* SD Active Video Length SD Chroma SD Burst SD Color Bars SD DAC Swap Reserved Reserved Mode Register SD PrPb Scale SD Y Scale SD Hue Adjust SD Brightness SD Luma SSAF Gain ...
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... LINE Figure 20. Timing Register 1 in PAL Mode –27– ADV7314 0 Slave mode 1 Master mode 0 Mode 0 1 Mode 1 0 Mode 2 1 Mode 3 Enabled Disabled No delay 2 clk cycles 4 clk cycles 6 clk cycles –40 IRE –7.5 IRE ...
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... ADV7314 SR7– SR0 Register Bit Description CGMS/WSS 0 SD CGMS Data SD CGMS CRC SD CGMS on Odd SD CGMS on Even SD WSS 5Ah SD CGMS/WSS 1 SD CGMS/WSS Data 5Bh SD CGMS/WSS 2 SD CGMS/WSS Data 5Ch SD LSB Register SD LSB for Y Scale SD LSB for U Scale SD LSB for V Scale ...
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... ADV7314 Reset Value Filter Filter B Filter C Filter D DNR mode DNR Sharpness mode 0 pixel offset 1 pixel offset … 14 pixel offset 15 pixel offset ...
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... ADV7314 SR7- SR0 Register Bit Description 7Dh Reserved Reserved Reserved Macrovision MV Control Bits Macrovision MV Control Bits Macrovision MV Control Bits Macrovision MV Control Bits Macrovision MV Control Bits Macrovision MV Control Bits Macrovision MV Control Bits ...
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... Address 0x7C, Bit 1 (Global 10-Bit Enable) Address 0x13, Bit 2 (HD 10-Bit Enable) Address 0x48, Bit 4 (SD 10-Bit Enable) Note that the ADV7314 defaults to simultaneous standard definition and progressive scan on power-up. Address[01h]: Input Mode = 011. Standard Definition Only Address [01h] Input Mode = 000 The 8-bit/10-bit multiplexed input data is input on Pins S9– ...
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... Figure 27. 1 –32– t 9.25ns OR DELAY t 27.75ns DELAY 3FF Cb0 Y0 Cr0 3FF Cb0 Y1 3FF Cb0 Y0 MPEG2 DECODER ADV7314 27MHz OR 54MHz YCrCb CLKIN_A INTERLACED YCrCb 10 TO Y[9:0] PROGRESSIVE P_VSYNC 3 P_HSYNC P_BLANK 10-Bit MHz or 54 MHz Y1 Cr0 Cr0 Y1 REV. 0 ...
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... Y9-Y0 [MSB = Y9] 8 4:2:2 YCrCb S9-S2 [MSB = S9] 16 4:2:2 Y Y9-Y2 [MSB = Y9] CrCb C9-C2 [MSB = C9] 10 4:2:2 YCrCb S9-S0 [MSB = S9] 20 4:2:2 Y Y9-Y0 [MSB = Y9] CrCb C9-C0 [MSB = C9] –33– ADV7314 Subaddress Register Setting 01h 00h 48h 00h 01h 00h 48h 10h 01h 00h 48h 08h 01h 00h 48h 18h 01h 80h 48h 00h ...
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... ADV7314 OUTPUT CONFIGURATION These tables show which output signals are assigned to the DACs when the control bits are set accordingly. RGB/YUV Output 02h, Bit RGB HD Input Input 15h, Format Bit 1 YCrCb 4:2:2 0 YCrCb 4:2:2 0 YCrCb 4:2:2 0 YCrCb 4:2:2 0 YCrCb 4:4:4 ...
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... Bit 3,2] For any input data that does not conform to the standards selectable in input mode, Subaddress 01h, asynchronous tim- ing mode can be used to interface to the ADV7314. Timing control signals for HSYNC, VSYNC, and BLANK have to be programmed by the user. Macrovision and programmable ...
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... ADV7314 P_HSYNC P_VSYNC P_BLANK* 1 -> -> -> -> -> 0 *When async timing mode is enabled, P_BLANK [Pin 25] becomes an active high input. P_BLANK is set to active low at Address 10h, Bit 6. For standards that do not require a tri-sync level, P_BLANK must be tied low at all times. ...
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... The field count register at Address 7Bh can be used to identify the number of the active field. RTC Mode In RTC mode, the ADV7314 can be used to lock to an external video source. The real-time control mode allows the ADV7314 to automatically alter the subcarrier frequency to compensate for line length variations ...
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... RTC TIME SLOT 01 NOTES 1 F PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7314 F SC PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7314. 2 SEQUENCE BIT PAL LINE NORMAL LINE INVERTED; NTSC CHANGE ...
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... Vertical Blanking Interval The ADV7314 accepts input data that contains VBI data [e.g., CGMS, WSS, VITS and HD modes. For SMPTE 293M [525p] standards, VBI data can be inserted on Lines each frame, or Lines for ITU-R BT.1358 [625p] standard. For SD NTSC, this data can be present on Lines 10 to 20, and in PAL on Lines 7 to 22. If VBI is disabled [Address 11h, Bit 4 for HD ...
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... ADV7314 FILTER SECTION Table VI shows an overview of the programmable filters avail- able on the ADV7314. Table VI. Selectable Filters of the ADV7314 Filter SD Luma LPF NTSC SD Luma LPF PAL SD Luma Notch NTSC SD Luma Notch PAL SD Luma SSAF SD Luma CIF SD Luma QCIF SD Chroma 0.65 MHz SD Chroma 1.0 MHz SD Chroma 1 ...
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... REV addition to the chroma filters listed in Table VII, the ADV7314 contains an SSAF filter specifically designed for and applicable to the color difference component outputs, U and V. This filter has a cutoff frequency of about 2.7 MHz and – ...
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... ADV7314–Typical Performance Characteristics PROG SCAN Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 FREQUENCY (MHz) TPC 1. PS – Oversampling Filter—Linear Y RESPONSE IN PS OVERSAMPLING MODE 0 –10 –20 –30 –40 –50 – ...
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... ADV7314 FREQUENCY (MHz) TPC 10. Luma PAL Low-Pass Filter FREQUENCY (MHz) TPC 11. Luma PAL Notch Filter ...
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... ADV7314 –2 –4 –6 –8 –10 – FREQUENCY (MHz) TPC 13. Luma SSAF Filter—Programmable Responses 1 0 –1 –2 –3 –4 – FREQUENCY (MHz) TPC 14. Luma SSAF Filter—Programmable Attenuation 0 –10 –20 –30 –40 –50 –60 –70 ...
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... ADV7314 FREQUENCY (MHz) TPC 22. Chroma 1.3 MHz LP Filter FREQUENCY (MHz) TPC 23. Chroma 0.65 MHz LP Filter FREQUENCY (MHz) TPC 24. Chroma QCIF LP Filter ...
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... Table IX. RGB Matrix Default Values 16 (10) 166 (A6) 202 (CA) When the programmable RGB matrix is not enabled, the ADV7314 automatically scales YCrCb inputs to all standards supported by this part. SD Luma and Color Control [Subaddresses 5Ch, 5Dh, 5Eh, 5Fh scale scale, and SD Cb scale are 10-bit control registers to scale the Y, U, and V output levels ...
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... The ADV7314 provides a range of ± 22.5H incre- ments of 0.17578125H. For normal operation (zero adjustment), this register is set to 80h. FFh and 00h represent the upper and lower limit (respectively) of adjustment attainable ...
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... ADV7314 PROGRAMMABLE DAC GAIN CONTROL DACs A, B, and C are controlled by Register 0A. DACs D, E, and F are controlled by Register 0B. 2 The I C control registers will adjust the output signal gain up or down from its absolute level. CASE A GAIN PROGRAMMED IN DAC O/P LEVEL REGISTERS, SUBADDRESS 0Ah, 0Bh ...
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... For example: *rounded to the nearest integer The gamma curves in Figure 41 are examples only; any user defined curve is acceptable in the range 240. 300 250 200 200 250 150 100 50 –49– ADV7314 È ˘ –16 = ¥ ...
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... ADV7314 HD Sharpness Filter Control and Adaptive Filter Control [Subaddress 20h, 38h–3Dh] There are three Filter modes available on the ADV7314: sharpness filter mode and two adaptive filter modes. HD Sharpness Filter Mode To enhance or attenuate the Y signal in the frequency ranges shown in Figure 42, the following register settings must be used: HD sharpness filter must be enabled and HD adaptive filter enable must be disabled ...
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... CH1 500mV M 4.00 s CH1 ALL FIELDS REF A 1 9.99978ms –51– ADV7314 Table XIII. Address Register Setting 00h FCh 01h 10h 02h 20h 10h 00h 11h 85h 20h 99h d ...
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... ADV7314 Adaptive Filter Control Application Figures 44 and 45 show a typical signal to be processed by the adaptive filter control block. Figure 44. Input Signal to Adaptive Filter Control Figure 45. Output Signal after Adaptive Filter Control The following register settings were used to obtain the results shown in Figure 45, i.e., to remove the ringing on the Y signal. ...
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... ADD SIGNAL ABOVE THRESHOLD RANGE FROM ORIGINAL SIGNAL + + DNR OUT –53– ADV7314 APPLY DATA APPLY BORDER CORING GAIN CORING GAIN OFFSET CAUSED BY VARIATIONS ...
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... ADV7314 Block Size Control [Address 64h, Bit 7] This bit is used to select the size of the data blocks to be processed. Setting the block size control function to a Logic 1 defines a 16 pixel ¥ 16 pixel data block; a Logic 0 defines an 8 pixel ¥ 8 pixel data block, where one pixel refers to two clock cycles at 27 MHz. DNR Input Select Control [Address 65h, Bit 2– ...
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... REV. 0 SAV/EAV Step Edge Control The ADV7314 can control fast rising and falling signals at the start and end of active video to minimize ringing. An algorithm monitors SAV and EAV and governs when the edges are too fast. The result will be reduced ringing at the start and end of active video for fast transitions ...
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... AD8061. More information on line driver buffering circuits is given in the relevant op amp data sheets. An optional analog reconstruction low-pass filter (LPF) may be required as an anti-imaging filter if the ADV7314 is connected to a device that requires this filtering. The filter specifications vary with the application. ...
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... Figure 57. Example for Output Filter for HDTV, 2 ¥ Oversampling Table XVII shows possible output rates from the ADV7314. Table XVII. Input Mode PLL Address 01h, Bit 6–4 Address 00h, Bit 1 Rate SD Only Off On PS Only ...
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... ADV7314 to minimize reflections. For optimum performance recommended that all decoupling and external components relating to the ADV7314 be located on the same side of the PCB and as close as possible to the ADV7314. Any unused inputs should be tied to ground. –58– ...
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... CLKIN_B P_HSYNC DAC F 150 P_VSYNC 100 SCLK P_BLANK 100 SDA RESET V DD ALSB CLKIN_A R SET2 3040 EXT_LF R SET1 3040 11, 57 Figure 60. ADV7314 Circuit Layout –59– ADV7314 1.1k RECOMMENDED EXTERNAL 100nF AD1580 FOR OPTIMUM PERFORMANCE ...
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... Bits C/W05 and C/W06 control whether or not CGMS data is output on odd and even fields. CGMS data can be transmitted only when the ADV7314 is configured in NTSC mode. The CGMS data is 20 bits long, and the function of each of these bits is as shown in Table XVIII. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit ...
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... Figure 63. HDTV 720P CGMS Waveform BIT 1 BIT .BIT C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 T 30ns 22.84 s 210ns 22T 1H Figure 64. HDTV 1080i CGMS Waveform –61– ADV7314 CRC SEQUENCE 21.2 s 0.22 s 22T T = 1/(f 33) = 963ns HORIZONTAL SCAN FREQUENCY H ...
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... The ADV7314 supports wide screen signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the ADV7314 is configured in PAL mode. The WSS data is 14 bits long, and the function of each of these bits is as shown in Table XIX. The WSS data is preceded ...
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... Scan Line 284. The data for this operation is stored in the SD closed captioning registers [Address 51h–52h]. All clock run-in signals and timing to support closed captioning on Lines 21 and 284 are generated automatically by the ADV7314. All pixels inputs are ignored during Lines 21 and 284 if closed captioning is enabled. ...
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... ADV7314 APPENDIX 4—TEST PATTERNS The ADV7314 can generate SD and HD test patterns CH2 200mV M 10 30.6000 s Figure 67. NTSC Color Bars T 2 CH2 200mV M 10 30.6000 s Figure 68. PAL Color Bars T 2 CH2 100mV M 10 Figure 69. NTSC Black Bar (–21 mV, 0 mV, 3.5 mV, 7 mV, 10.5 mV, 14 mV, 18 mV, 23 mV) A CH2 1 ...
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... For 625p black bar pattern output on DAC D, the same settings are used as for a 625p hatch pattern except that subaddress = 02h and register setting = 24h; and subaddress = 10h and register setting = 50h. –65– ADV7314 CH2 100mV M 4.0 s CH2 EVEN T 1 ...
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... Mode 0 (CCIR-656)—Slave Option (Timing Register 0 TR0 = The ADV7314 is controlled by the SAV (start active video) and EAV (end active video) time codes in the pixel data. All timing information is transmitted using a 4-byte synchronization pat- tern. A synchronization pattern is sent immediately before and after each line during active picture and retrace ...
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... Mode 0 (CCIR-656)—Master Option (Timing Register 0 TR0 = The ADV7314 generates H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes in the CCIR656 standard. The H bit is output on S_HSYNC, the V bit is output on S_BLANK, and the F bit is output on S_VSYNC pin ...
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... A transition of the field input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7314 automatically blanks all normally blank lines as per CCIR-624. HSYNC is input on HSYNC, BLANK on S_BLANK, and FIELD on S_VSYNC. ...
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... Mode 1—Master Option (Timing Register 0 TR0 = this mode, the ADV7314 can generate horizontal sync and odd/ even field signals. A transition of the field input when HSYNC is low indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7314 automatically blanks all normally blank lines as per CCIR-624 ...
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... ADV7314 Mode 2—Slave Option (Timing Register 0 TR0 = this mode, the ADV7314 accepts horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transi- tion when HSYNC is high indicates the start of an even field. ...
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... Mode 2—Master Option (Timing Register 0 TR0 = this mode, the ADV7314 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field ...
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... ADV7314 Mode 3—Master/Slave Option (Timing Register 0 TR0 = this mode, the ADV7314 accepts or generates horizontal sync and odd/even field signals. A transition of the field input when HSYNC is high indicates a new frame i.e., vertical re- trace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7314 automatically blanks all normally blank lines as per CCIR-624 ...
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... FIELD 2 561 562 563 P_VSYNC P_HSYNC REV. 0 VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 567 568 565 566 564 Figure 90. 1080i HSYNC and VSYNC Input Timing –73– ADV7314 DISPLAY 560 7 20 DISPLAY 1123 569 583 584 585 570 ...
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... ADV7314 APPENDIX 7—VIDEO OUTPUT LEVELS HD YPrPb Output Levels EIA-770.2, STANDARD FOR Y INPUT CODE 940 64 EIA-770.2, STANDARD FOR Pr/Pb 960 512 64 Figure 91. EIA 770.2 Standard Output Signals (525p/625p) EIA-770.1, STANDARD FOR Y INPUT CODE 940 64 EIA-770.1, STANDARD FOR Pr/Pb 960 512 64 Figure 92. EIA 770.1 Standard Output Signals ...
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... Figure 97. SD RGB Output Levels—RGB Sync Disabled 300mV 0mV 550mV 300mV 0mV 550mV 300mV 0mV Figure 98. SD RGB Output Levels—RGB Sync Enabled –75– ADV7314 700mV 550mV 700mV 550mV 700mV 550mV 700mV 550mV 550mV 700mV 550mV 700mV ...
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... ADV7314 YPrPb Output Levels 280mV 220mV 160mV 60mV Figure 99. U Levels—NTSC 280mV 220mV 160mV 60mV Figure 100. U Levels—PAL 200mV 1260mV 1000mV 140mV Figure 101. U Levels—NTSC 332mV 110mV 332mV 110mV 2150mV 900mV –76– 2150mV 200mV 1260mV 1000mV 900mV 140mV Figure 102. U Levels— ...
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... REV L76 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS Figure 105. NTSC Color Bars 75 L76 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS Figure 106. NTSC Chroma –77– ADV7314 50 60 SYNC = A FRAMES SELECTED SYNC = B FRAMES SELECTED 1 2 ...
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... ADV7314 VOLTS IRE:FLT 0.6 0.4 0.2 0 –0.2 10 NOISE REDUCTION: 15.05dB APL = 44.3% 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00 AT 6.72 s VOLTS 0.6 0.4 0.2 0 –0.2 0 NOISE REDUCTION: 0.00dB APL = 39.1% 625 LINE NTSC NO FILTERING SLOW CLAMP TO 0. L238 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS Figure 107. NTSC Luma ...
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... MICROSECONDS NO BUNCH SIGNAL PRECISION MODE OFF SYNCHRONOUS Figure 109. PAL Chroma L575 MICROSECONDS NO BUNCH SIGNAL PRECISION MODE OFF SYNCHRONOUS Figure 110. PAL Luma –79– ADV7314 50 60 SOUND-IN-SYNC OFF FRAMES SELECTED SOUND-IN-SYNC OFF FRAMES SELECTED 1 ...
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... ADV7314 APPENDIX 8—VIDEO STANDARDS SMPTE 274M ANALOG WAVEFORM 4T EAV CODE INPUT PIXELS CLOCK SAMPLE NUMBER 2112 2116 2156 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562 SAV/EAV: LINE 563–1125 SAV/EAV: LINE 1–20; 561–583; 1124–1125 SAV/EAV: LINE 21– ...
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... Figure 115. SMPTE 296M (720p) VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 563 564 565 566 567 568 569 Figure 116. SMPTE 274M (1080i) –81– ADV7314 ACTIVE VIDEO ACTIVE VIDEO DISPLAY 8 ...
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... ADV7314 64-Lead Low Profile Quad Flat Package [LQFP 1.40 1.35 0.15 SEATING 0.05 0.10 MAX PLANE COPLANARITY VIEW A ROTATED 90 CCW OUTLINE DIMENSIONS (ST-64) Dimensions shown in millimeters 0.75 12.00 BSC 1.60 0.60 MAX 0. SEATING PIN 1 PLANE TOP VIEW (PINS DOWN) 0.20 0.09 VIEW 0.50 BSC COMPLIANT TO JEDEC STANDARDS MS-026BCD –82– ...
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