cat522 Catalyst Semiconductor, cat522 Datasheet - Page 7

• Manufacturer Part Number: cat522
• Description: Configured Digitally Programmable Potentiometer Dpp? Programmable Voltage Applications
• Manufacturer: Catalyst Semiconductor

No clock is necessary upon system power-up. The
CAT522’s internal power-on reset circuitry loads data
from non-volatile memory to the DPPs without using
the external clock.
As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking
data into the control registers. Standard CMOS and
TTL logic families work well in this regard and it is
recommended that any mechanical switches used for
breadboarding or device evaluation purposes be
debounced by a flip-flop or other suitable debouncing
circuit.
V
V
sets the DPP’s Zero to Full Scale output range where
V
the full power supply range or just a fraction of it. In
typical applications V
across the power supply rails. When using less than
the full supply voltage be mindfull of the limits placed
on V
section of DC Electrical Characteristics.
READY/BUSY
When saving data to non-volatile memory, the
Ready/Busy ouput (RDY/BSY
duration of the erase/write cycle. Upon receiving a
command to store data (PROG goes high) RDY/BSY
goes low and remains low until the programming cycle is
complete. During this time the CAT521 will ignore any
data appearing at DI and no data will be output on DO.
RDY/BSY
detector circuit monitoring V
minimum value required for non-volatile programming,
Figure 1. Writing to Memory
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
REF
REF
REFL
, the voltage applied between pins V
REFH
¯¯¯¯ is internally ANDed with a low voltage
= Zero and V
¯¯¯¯¯
and V
REFL
REFH
as specified in the References
REFH
= Full Scale. V
¯¯¯¯ ) signals the start and
& V
DD.
RDY/BSY
OUTPUT
PROG
DPP
DO
CS
DI
REFL
If V
DD
t
are connected
o
1
REF
is below the
REFH
1
2
A0
can span
3
& V
A1
4
NON-VOL ATILE
DPP VALUE
CURRENT
D0
D0
5
¯¯¯¯
REFL
6
D1
D1
7
CURRENT DPP DATA
NEW DPP DATA
D2
D2
,
8
D3
D3
7
9
D4
D4
10
RDY/BSY
command indicating a failure to record the desired
data in non-volatile memory.
DATA OUTPUT
Data is output serially by the CAT522, LSB first, via
the Data Out (DO) pin following the reception of a
start bit and two address bits by the Data Input (DI).
DO becomes active whenever CS goes high and
resumes its high impedance Tri-State mode when CS
returns low.
522s to share a single serial data line and simplifies
interfacing multiple 522s to a microprocessor.
WRITING TO MEMORY
Programming the CAT522’s non-volatile memory is
accomplished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DPP address and eight data bits
are clocked into the DPP wiper control register via the
DI pin. Data enters on the clock’s rising edge. The
DPP output changes to its new setting on the clock
cycle following D7, the last data bit.
Programming is accomplished by bringing PROG high
sometime after the start bit and at least 150 ns prior to
the rising edge of the clock cycle immediately following
the D7 bit. Two clock cycles after the D7 bit the DPP
wiper control register will be ready to receive the next
set of address and data bits. The clock must be kept
running throughout the programming cycle.
control circuitry takes care of generating and ramping
up the programming voltage for data transfer to the
non-volatile cells. The CAT522’s non-volatile memory
cells will endure over 1,000,000 write cycles and will
retain data for a minimum of 100 years without being
refreshed.
D5
D5
D6
D6
11
¯¯¯¯ will remain high following the program
D7
D7
12
DPP VALUE
VOLATILE
NEW
N
Tri-Stating the DO pin allows several
N+1 N+2
NON-VOL ATILE
DPP VALUE
NEW
Doc. No. MD-2004 Rev. G
CAT522
Internal