cat5270 ON Semiconductor, cat5270 Datasheet - Page 5

• Manufacturer Part Number: cat5270
• Description: Dual Digitally Programmable Potentiometers Dpp With 256 Taps & I2c Compatible Interface
• Manufacturer: ON Semiconductor

Serial Bus Protocol
interface protocol:
processor or controller, and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations.
Therefore, the CAT5270 will be considered a slave device
in all applications.
START Condition
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH (see Figure 3). The CAT5270 monitors
the SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
determines the STOP condition (see Figure 3). All
operations must end with a STOP condition.
Device Addressing
START condition. The Master then sends the Slave Addres
Byte which contains the address of the particular slave
device it is requesting. The four most significant bits of the
8−bit slave address are fixed as 0101 for the CAT5270. The
next four significant bits (A3, A2, A1, A0) are the device
address bits and define which device the Master is accessing
(see Figure 5). Up to sixteen devices may be individually
addressed by the system. Typically, +5 V (V
are hard−wired to these pins to establish the device’s
address.
The following defines the features of the I
The device controlling the transfer is a master, typically a
The START Condition precedes all commands to the
A LOW to HIGH transition of SDA when SCL is HIGH
The bus Master begins a transmission by sending a
SDA OUT
1. Data transfer may be initiated only when the bus is
2. During a data transfer, the data line must remain
SDA IN
not busy.
stable whenever the clock line is high. Any
changes in the data line while the clock is high
will be interpreted as a START or STOP condition.
SCL
t
SU:STA
t
F
t
HD:STA
t
LOW
CC
t
2
AA
C compatible
) and ground
t
HD:DAT
t
HIGH
Figure 2. Bus Timing
http://onsemi.com
t
LOW
5
t
DH
address byte, the CAT5270 monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address.
Slave Address Byte
device type identifier. These bits for the CAT5270 are fixed
at 0101[B] (refer to Figure 5).
and must match the physical device address which is defined
by the state of the A3 − A0 input pins for the CAT5270 to
successfully continue the command sequence. Only the
device which slave address matches the incoming device
address sent by the master executes the instruction. The A3
− A0 inputs can be actively driven by CMOS input signals
or tied to V
Acknowledge
required to generate an acknowledge. The Acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data (see Figure 4).
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8−bit
byte.
of data, releases the SDA line, and monitors the line for an
acknowledge. Once it receives this acknowledge, the
CAT5270 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition.
it will no longer responds with acknoleadge as the received
data it is not in a byte format.
After the Master sends a START condition and the slave
The most significant four bits of the slave address are a
The next four bits, A3 − A0, are the internal slave address
After a successful data transfer, each receiving device is
The CAT5270 responds with an acknowledge after
When the CAT5270 is in a READ mode it transmits 8 bits
If the device has been selected with an IN/DEC operation
t
SU:DAT
t
R
CC
or V
SS
.
t
t
BUF
SU:STO