bh2226fv ROHM Co. Ltd., bh2226fv Datasheet - Page 5

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bh2226fv

Manufacturer Part Number
bh2226fv
Description
Expansion Port Function Built In 8 Bit 8chd/a Converter
Manufacturer
ROHM Co. Ltd.
Datasheet

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・Command Transmission Procedures
Carry out the following after power on and just after external reset:
(1) Power Down Release (2) I/O D/A Select (3) I/O Status Set
Note: When power is started, the power on reset is activated and the internal register initialized. However, as shown in the
figure above, in area (a), if CSB cannot be made High and noise is introduced in the control line an error may occur when
setting during the rising CSB signal.
In such a case, set the external RESETB terminal to Low and reset when CSB = High.
・Parallel - Serial Conversion
・Serial - Parallel Conversion
DI serial data is taken in at the rising edge of the CLK.
The data is then output from the DA[8:1] terminal just after the CSB rising edge.
During that time the SO terminal output becomes undetermined (just previous address setting + data output).
・D/A Converter Output Setting (Fig. 7)
DI serial data is taken in at the rising edge of the clock.
The D/A converter output is output from the DA[8:1] terminal just after the rising edge of the CSB.
During that time, the SO terminal output becomes undetermined (just previous address setting + data output).
Parallel data {DA[8:1]} is taken in at the first CSB falling edge after setting the parallel serial command.
The data is then outputted in synch with the falling edge of the CLK in the next CSB = Low area, and output from 4CLK.
However, please note that the SCLK falling edge that occurs from CSB fall to the first SCLK rising edge is not counted.
PS conversion command
Power down release
Parallel data taking in
5/8
Fig.4
Fig.7
I/O DAC select
Fig.5
Fig.6
I/O status setting
Arbitrary setting
DAC output
DA1 output
Parallel data output

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