adsp-21061l Analog Devices, Inc., adsp-21061l Datasheet - Page 44

• Manufacturer Part Number: adsp-21061l
• Description: Commercial Grade Sharc Family Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-21061/ADSP-21061L
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by ΔV is dependent on the capacitive load, C
load current, I
following equation:
The output disable time t
t
the interval from when the reference signal switches to when the
output voltage decays ΔV from the measured output high or
output low voltage. t
and with ΔV equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driv-
ing. The output enable time t
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
to be the difference between the ADSP-21061’s output voltage
and the input threshold for the device requiring the hold time. A
typical ΔV will be 0.4 V. C
line), and I
line). The hold time will be t
time (i.e., t
MEASURED
REFERENCE
V
V
OH (MEASURED)
OL (MEASURED)
SIGNAL
and t
DATRWH
L
is the total leakage or three-state current (per data
t
DIS
DECAY
L
OUTPUT STOPS
DECAY
. This decay time can be approximated by the
DRIVING
for the write cycle).
Figure 27. Output Enable/Disable
as shown in
using the equation given above. Choose ΔV
DECAY
t
MEASURED
V
V
OH (MEASURED)
OL (MEASURED)
t
P
DECAY
DIS
is calculated with test loads C
EXT
L
is the total bus capacitance (per data
is the difference between
DECAY
ENA
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V.
=
Figure
is the interval from when a
C L V
-------------- -
plus the minimum disable
- V
+ V
I
Δ
L
27. The time t
(Figure
OUTPUT STARTS
t
ENA
1.0V
2.0V
DRIVING
27). If multiple
V
V
OH (MEASURED)
OL (MEASURED)
MEASURED
Rev. C | Page 44 of 56 | July 2007
L
, and the
L
and I
is
L
,
Output Drive Characteristics
Figure 30
output drivers of the ADSP-21061 (5 V) and ADSP-21061L
(3 V). The curves represent the current drive capability and
switching behavior of the output drivers as a function of
resistive and capacitive loading.
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF.
Figure
varies with capacitance.
cally how output delays and holds vary with load capacitance.
(Note that this graph or derating does not apply to output dis-
able delays; see the previous section Output Disable Time under
Test Conditions.) The graphs of
and
Figure 28. Equivalent Device Loading for AC Measurements (Includes All
Figure 29. Voltage Reference Levels for AC Measurements (Except Output
OUTPUT
Figure 36
32,
PIN
TO
OUTPUT
INPUT
through
OR
Figure
50pF
may not be linear outside the ranges shown.
35, and
Figure 37
Figure
1.5V
Figure 33
Enable/Disable)
Figure 36
I
I
OH
OL
Fixtures)
show typical characteristics for the
28). The delay and hold specifica-
Figure
and
show how output rise time
Figure 37
31,
1.5V
1.5V
Figure
Figure
show graphi-
32,
31,
Figure
35,