adsp-2165ks-80 Analog Devices, Inc., adsp-2165ks-80 Datasheet - Page 6

• Manufacturer Part Number: adsp-2165ks-80
• Description: Dsp Microcomputers With Rom
• Manufacturer: Analog Devices, Inc.

Pin
Name(s)
Address
Data
RESET
IRQ2
BR
BG
PMS
DMS
BMS
RD
WR
MMAP
CLKIN, XTAL
CLKOUT
V
GND
SPORT0
SPORT1
or Interrupts and Flags:
NOTES
1
2
3
ADSP-216x
A clock output signal (CLKOUT) is generated by the processor,
synchronized to the processor’s internal cycles.
Reset
The RESET signal initiates a complete reset of the ADSP-216x.
The RESET signal must be asserted when the chip is powered
up to assure proper initialization. If the RESET signal is applied
during initial power-up, it must be held long enough to allow
the processor’s internal clock to stabilize. If RESET is activated
at any time after power-up and the input clock frequency does
not change, the processor’s internal clock continues and does
not require this stabilization time.
Unused data bus lines may be left floating.
BR must be tied high (to V
Only on ADSP-2165/ADSP-2166.
DD
IRQ0 (RFS1)
IRQ1 (TFS1)
FI (DR1)
FO (DT1)
PWDACK
PWDFLAG
2
1
Figure 2. External Crystal Connections
3
3
CLKIN
ADSP-216x
DD
) if not used.
XTAL
# of
Pins
14
24
1
1
1
1
1
1
1
1
1
1
2
1
5
5
1
1
1
1
1
1
CLKOUT
Input/
Output
O
I/O
I
I
I
O
O
O
O
O
O
I
I
O
I/O
I/O
I
I
I
O
O
I
PIN FUNCTION DESCRIPTIONS
–6–
Function
Address outputs for program, data and boot memory.
Data I/O pins for program and data memories. Input only for
boot memory, with two MSBs used for boot memory addresses.
Unused data lines may be left floating.
Processor Reset Input
External Interrupt Request #2
External Bus Request Input
External Bus Grant Output
External Program Memory Select
External Data Memory Select
Boot Memory Select
External Memory Read Enable
External Memory Write Enable
Memory Map Select Input
External Clock or Quartz Crystal Input
Processor Clock Output
Power Supply Pins
Ground Pins
Serial Port 0 Pins (TFS0, RFS0, DT0, DR0, SCLK0)
Serial Port 1 Pins (TFS1, RFS1, DT1, DR1, SCLK1)
External Interrupt Request #0
External Interrupt Request #1
Flag Input Pin
Flag Output Pin
Indicates when the processor has entered power-down.
Low-to-High Transition of the Power-Down Flag. Input pin can
be used to terminate power-down.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
applied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 t
not, however, include the crystal oscillator start-up time).
During this power-up sequence the RESET signal should be
held low. On any subsequent resets, the RESET signal must
meet the minimum pulsewidth specification, t
To generate the RESET signal, use either an RC circuit with an
external Schmidt trigger or a commercially available reset IC.
(Do not use only an RC circuit.)
The RESET input resets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, the boot loading sequence is
performed (provided there is no pending bus request and the chip
is configured for booting, with MMAP = 0). The first instruction is
then fetched from internal program memory location 0x0000.
CK
cycles will ensure that the PLL has locked (this does
RSP
.
DD
is
REV. 0