adsp-2196m Analog Devices, Inc., adsp-2196m Datasheet - Page 36

• Manufacturer Part Number: adsp-2196m
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-2196
Host Port ACC Mode Write Cycle Timing
Table 15
on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description
Table 15. Host Port ACC Mode Write Cycle Timing
1
36
t
the same time.
Parameter
Switching Characteristics
t
t
t
t
Timing Requirements
t
t
t
t
t
t
t
t
t
t
t
t
t
NH
WHKS
WHKH
WHS
WHH
WAL
CSAL
ALCS
WCSW
ALW
CSW
WCS
ALEW
HKWD
ADW
WAD
DWS
WDH
are peripheral bus latencies (n t
and
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
Figure 18
Description
HWR asserted to HACK asserted (setup, ACK Mode)
HWR de-asserted to HACK de-asserted (hold, ACK Mode)
HWR asserted to HACK asserted (setup, Ready Mode)
HWR asserted to HACK de-asserted (hold, Ready Mode)
HWR asserted to HALE de-asserted (delay)
HCMS or HCIOMS asserted to HALE asserted (delay)
HALE de-asserted to optional HCMS or HCIOMS
de-asserted
HWR de-asserted to HCMS or HCIOMS de-asserted
HALE asserted to HWR asserted
HCMS or HCIOMS asserted to HWR asserted
HWR de-asserted (after last byte) to HCMS or
HCIOMS de-asserted (ready for next write)
HALE de-asserted to HWR asserted
HACK asserted to HWR de-asserted (hold, ACK Mode)
Address valid to HWR asserted (setup)
HWR de-asserted to address invalid (hold)
Data valid to HWR de-asserted (setup)
HWR de-asserted to data invalid (hold)
describe host port write operations in Address Cycle Control (ACC) mode. For more information
HCLK
For current information contact Analog Devices at 800/262-5643
); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at
Min
0.6
1.5
0
1
1
0.5
1
1
1
1.5
4
1
4
1
on page
10.
September 2001
Max
0.6+t
2
0.6
2+t
2
NH
NH
1
1
REV. PrA
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns