dsp56362 Freescale Semiconductor, Inc, dsp56362 Datasheet
dsp56362
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dsp56362 Summary of contents
Page 1
... DSPs while retaining code compatibility. Significant architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and direct memory access (DMA). The DSP56362 offers 100 million instructions per second (MIPS) using an internal 100 MHz clock at 3.3 V. This document contains information on a new product. Specifications and information herein are subject to change without notice. ...
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... YDB XDB PDB GDB Program Program 24 ¥ Æ 56-bit MAC Decode Address Two 56-bit Accumulators Controller Generator MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD Figure 1-1 DSP56362 Block Diagram DSP56362 Technical Data, Rev. 4 Signal State Voltage* Asserted Deasserted Asserted ...
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... Triggering from interrupt lines and all peripherals — Phase-locked loop (PLL) – Software programmable PLL-based frequency synthesizer for the core clock – Allows change of low-power divide factor (DF) without loss of lock – Output clock with skew elimination — Hardware debugging support Freescale Semiconductor DSP56362 Technical Data, Rev. 4 Overview 1-3 ...
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... DSP56362 Technical Data, Rev Data RAM Size Y Data RAM Size 5632 × 24-bit 5632 × 24-bit 5632 × 24-bit 5632 × 24-bit 5632 × 24-bit 3584 × ...
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... Documentation lists the documents that provide a complete description of the DSP56362 and are required to Table 1-1 design properly with the part. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, a Freescale Literature Distribution Center, or through the Freescale DSP home page on the Internet (the source for the latest information) ...
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... Overview 1-6 NOTES DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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... The input and output signals of the DSP56362 are organized into functional groups, which are listed in Table 2-1 and illustrated in Figure The DSP56362 is operated from a 3.3 V supply; however, some of the inputs can tolerate special notice for this feature is added to the signal descriptions of those inputs. Table 2-1 DSP56362 Functional Signal Groupings Functional Group ...
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... SDO1 SDO0 Digital Audio ACI 2 Transmitter (DAX) ADO 2 Timer 0 TIO0 TCK TDI TDO JTAG/OnC TMS E Port TRST DE DSP56362 Technical Data, Rev. 4 Multiplexed Port B Bus GPIO HAD0–HAD7 PB0–PB7 HAS/HAS PB8 HA8 PB9 HA9 PB10 HA10 PB13 Double DS HRD/HRD PB11 HWR/HWR ...
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... I/O drivers. This input must be CCC inputs. CCC is an isolated power for the HDI08 I/O drivers. This input must be tied externally CCH input. CCH is an isolated power for the SHI, ESAI, DAX, and Timer CCS DSP56362 Technical Data, Rev. 4 Power power rail. There is one CC inputs. CCS 2-3 ...
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... If the PLL is enabled and both the multiplication and division factors equal one, then CLKOUT is also synchronized to EXTAL. If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL. CLKOUT is not functional at frequencies of 100 MHz and above. DSP56362 Technical Data, Rev 0.47 µF capacitor P connection. ...
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... Input PINIT/NMI Input Input 2.5 External Memory Expansion Port (Port A) When the DSP56362 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant port A signals: A0–A17, D0–D23, AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS. 2.5.1 External Address Bus Signal Name Type State during Reset A0– ...
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... Otherwise, the signals are tri-stated. Transfer Acknowledge—If the DSP56362 is the bus master and there is no external bus activity, or the DSP56362 is not the bus master, the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2 ...
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... DSP requests bus mastership deasserted when the DSP no longer needs the bus. BR may be asserted or deasserted independent of whether the DSP56362 is a bus master or a bus slave. Bus “parking” allows deasserted even though the DSP56362 is the bus master. ...
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... MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. If IRQC is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQC to exit the wait state. This input tolerant. DSP56362 Technical Data, Rev. 4 Signal Description Freescale Semiconductor ...
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... MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted during power up. A stable EXTAL signal must be supplied while RESET is being asserted. This input tolerant. DSP56362 Technical Data, Rev. 4 Host Interface (HDI08) Signal Description 2-9 ...
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... Port B 9—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input tolerant. DSP56362 Technical Data, Rev. 4 Signal Description Freescale Semiconductor ...
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... Port B 12—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input tolerant. DSP56362 Technical Data, Rev. 4 Host Interface (HDI08) Signal Description 2-11 ...
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... Port B 13—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input tolerant. DSP56362 Technical Data, Rev. 4 Signal Description Freescale Semiconductor ...
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... Port B 15—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input tolerant. DSP56362 Technical Data, Rev. 4 Host Interface (HDI08) Signal Description 2-13 ...
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... SDA while SCL is high is a unique situation defined as the stop event. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input tolerant. DSP56362 Technical Data, Rev. 4 Signal Description 2 C bus transactions in the through a pull-up resistor. ...
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... This signal is tri-stated during hardware, software, personal reset, or when the HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for external pull-up in this state. This input tolerant. DSP56362 Technical Data, Rev. 4 Serial Host Interface Signal Description 2 C slave mode, the 2 C master mode ...
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... IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. Port C 1—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input tolerant. DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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... RX0 serial receive shift register. Port C 6—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input tolerant. DSP56362 Technical Data, Rev. 4 Enhanced Serial Audio Interface 2-17 ...
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... The default state after reset is GPIO disconnected. This input tolerant. serial transmit shift register. Port C 11—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input tolerant. DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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... GPIO output immediately at the beginning of operation or leave it defined as GPIO input but connected it to Vcc through a pull-up resistor in order to ensure a stable logic level at the input. This input tolerant. DSP56362 Technical Data, Rev. 4 Digital Audio Interface (DAX) Signal Description Signal Description 2-19 ...
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... All other interface with the OnCE module must occur through the JTAG port. The use not recommended for new designs recommended to leave DE disconnected. This input is not 5 V tolerant. DSP56362 Technical Data, Rev. 4 Signal Description Freescale Semiconductor ...
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... Introduction The DSP56362 is fabricated in high density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs. The DSP56362 specifications are preliminary and are from design simulations, and may not be fully tested or guaranteed. Finalized specifications will be published after full characterization and device qualifications are complete. ...
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... R θJA or θ R θJC Ψ JT Table 3-3 DC Electrical Characteristics Symbol IHP ) pins V 0.8 × V IHX pins V ILP V ILX DSP56362 Technical Data, Rev Value − +105 − +125 LQFP Value 45.3 JA 10.1 JC 5.5 1 Min Typ Max 3.14 3.3 3.46 2.0 — 2.0 — ...
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... Note 6 of the previous table. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal's transition. DSP56362 output levels are measured with the production test machine V at 0.4 V and 2.4 V, respectively. Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15 MHz and rated speed ...
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... DF/ — 0.49 × ET × PDF × C DF/MF 0.47 × ET × PDF × C DF/MF T — — — CYC DSP56362 Technical Data, Rev Expression Typ Max (Ef × MF)/(PDF × DF) — Ef/2 — ET — C 0.51 × ET × PDF × — C DF/MF 0.53 × ET × PDF × — ...
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... EXTERNAL CLOCK OPERATION The DSP56362 system clock is an externally supplied square wave voltage source connected to EXTAL (Figure 3-1) EXTAL ETH V ILC CLKOUT With PLL Disabled CLKOUT With PLL Enabled 6a Note: The midpoint is 0.5 (V Table 3-5 Clock Operation 100 and 120 MHz Values No. ...
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... CYC and maximum MF. CO and maximum DF. CO Table 3-6 PLL Characteristics Min × 2/PDF CCP PCAP (MF × 580) − 100 MF × 830 DSP56362 Technical Data, Rev. 4 100 MHz 120 MHz Min Max Min 0.0 ns 1.8 ns 0.0 ns 1.8 ns 0.0 ns 1.8 ns ∞ 0.00 ns 8.53 µs 8.53 µs 0.00 ns 100 MHz ...
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... C 5 3.25 × 2.0 C 20. 7. 3.25 × 2.0 C 20. 7.5 C 4.25 × 2.0 C 7.25 × 2 × 5.0 C DSP56362 Technical Data, Rev 100 MHz 120 MHz Unit Min Max Min Max — 26.0 26.0 500.0 — 416.7 — 10.0 — 8.3 — 750 — 625 — 750 — ...
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... PDF + C (23.75 ± 0.5) × T (8.25 ± 0.5) × PLC × ET × PDF + C (128K − PLC/2) × T PLC × ET × PDF + C (20.5 ± 0.5) × T 5.5 × DSP56362 Technical Data, Rev (continued) 100 MHz 120 MHz Min Max Min Max 7 – — Note — Note 7 C – ...
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... Reset, Stop, Mode Select, and Interrupt Timing 2 Expression 12T 12T 4.25 × 2 DSP56362 Technical Data, Rev (continued) 100 MHz 120 MHz Min Max Min Max — 120.0 — 100.0 — 80.0 — 66.7 — 80.0 — 66.7 — 120.0 — 100.0 — ...
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... Reset, Stop, Mode Select, and Interrupt Timing RESET 8 All Pins A0–A17 CLKOUT 11 RESET A0–A17 3-10 9 Reset Value Figure 3-2 Reset Timing 12 Figure 3-3 Synchronous Reset Timing DSP56362 Technical Data, Rev First Fetch AA0460 AA0461 Freescale Semiconductor ...
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... NMI Figure 3-5 External Interrupt Timing (Negative Edge-Triggered) Freescale Semiconductor First Interrupt Instruction Execution/Fetch First Interrupt Instruction Execution 18 b) General Purpose I/O Figure 3-4 External Fast Interrupt Timing 15 16 DSP56362 Technical Data, Rev. 4 Reset, Stop, Mode Select, and Interrupt Timing AA0462 AA0463 3-11 ...
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... MODC, MODD, PINIT IRQA A0–A17 Figure 3-8 Recovery from Stop State Using IRQA 3- Figure 3-7 Operating Mode Select Timing 24 25 DSP56362 Technical Data, Rev AA0464 IRQA, IRQB IRQC, IRQD, NMI V IL AA0465 First Instruction Fetch AA0466 Freescale Semiconductor ...
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... RD WR IRQA, IRQB, IRQC, IRQD, NMI Figure 3-10 External Memory Access (DMA Source) Timing Freescale Semiconductor 26 25 DMA Source Address 29 First Interrupt Instruction Execution DSP56362 Technical Data, Rev. 4 Reset, Stop, Mode Select, and Interrupt Timing First IRQA Interrupt Instruction Fetch AA0467 AA1104 3-13 ...
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... WS ≤ 3] 1.25 × T − 2 ≤ WS ≤ 7] 2.25 × T − 2.0 C [WS ≥ 8] All frequencies: 1.25 × T − 4 ≤ WS ≤ 7] 2.25 × T − 4.0 C [WS ≥ 8] DSP56362 Technical Data, Rev 100 MHz 120 MHz 2 Min Max Min Max 16.0 — 12.0 — 56.0 — 46.0 — 106.0 — ...
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... T [ 0.25 × ≤ WS ≤ 3] −0.25 × T [WS ≥ 4] 0.25 × ≤ WS ≤ 3] 1.25 × ≤ WS ≤ 7] 2.25 × T [WS ≥ 8] DSP56362 Technical Data, Rev. 4 External Memory Expansion Port (Port A) 1 (continued) 100 MHz 120 MHz 2 Min Max Min Max — 10.5 7.6 − ...
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... C 100 MHz: (WS + 0.25) × 100 MHz: 0.25 × T − 2 ≤ WS ≤ 3] 1.25 × T − 2 ≤ WS ≤ 7] 2.25 × T − 2.0 C [WS ≥ 8] DSP56362 Technical Data, Rev (continued) 100 MHz 120 MHz 2 Min Max Min Max — — 6.4 — — — 14.7 — ...
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... WR TA D0–D23 Freescale Semiconductor Symbol Expression 5 0.25 × 100 113 116 115 105 104 119 Figure 3-11 SRAM Read Access DSP56362 Technical Data, Rev. 4 External Memory Expansion Port (Port A) 1 (continued) 100 MHz 120 MHz 2 Min Max Min Max + 2.0 4.5 — 4.1 — 0 — ...
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... Figure 3-12 SRAM Write Access Figure 3-13 and Figure 3-16 should be used for primary selection only. DSP56362 Technical Data, Rev. 4 103 118 111 109 Data Out AA0469 Freescale Semiconductor ...
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... T CAC C 1.5 × T − 7 OFF 0.75 × RSH C 2 × T − 4.0 t RHCP C DSP56362 Technical Data, Rev. 4 External Memory Expansion Port (Port A) Chip Frequency (MHz) AA0472 MHz MHz Min Max Min Max 100.0 — 66.7 — 62.5 — 41.7 — ...
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... − 4 WCS C 1.5 × T − 4.0 t ROH C − 7 0.75 × 0.25 × T DSP56362 Technical Data, Rev (continued) 30 MHz MHz Min Max Min Max − 4.0 33.5 — 21.0 — − 6.0 81.5 — 52.3 — − 6.0 156.5 — 102.2 — ...
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... CRP ASC t CAH t RAL t RCS t RCH t WCH RWL t CWL WCS t ROH DSP56362 Technical Data, Rev MHz Expression Unit Min Max 3 × T 37.5 — 2. 34.4 — 1.5 × T − 6.5 — 12 2.5 × T − 6.5 — 24 0.0 — ...
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... The number of wait states for Page mode access is specified in the DCR. 2 The refresh period is specified in the DCR. 3 The asynchronous delays specified in the expressions are valid for DSP56362. 4 All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t read-after-read or write-after-write sequences). ...
Page 49
... The number of wait states for Page mode access is specified in the DCR. 2 The refresh period is specified in the DCR. 3 The asynchronous delays specified in the expressions are valid for DSP56362. 4 All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t read-after-read or write-after-write sequences). ...
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... C t 100 MHz: RCS 1.25 × 100 MHz: RCH 1.25 × T 3.25 × WCH 4.5 × 4.75 × RWL 3.75 × CWL DSP56362 Technical Data, Rev 100 MHz 120 MHz Min Max Min Max 50.0 — 41.7 C 45.0 — 37.5 C — 20.5 — 15.9 − 7.0 C — ...
Page 51
... The number of wait states for Page mode access is specified in the DCR. 2 The refresh period is specified in the DCR. 3 The asynchronous delays specified in the expressions are valid for DSP56362. 4 All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t read-after-read or write-after-write sequences). ...
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... Figure 3-14 DRAM Page Mode Write Accesses 3-26 131 137 139 140 141 Column Column Address Address 151 144 145 146 155 150 149 Data Out Data Out DSP56362 Technical Data, Rev. 4 136 135 138 142 Last Column Address 143 147 148 156 Data Out AA0473 Freescale Semiconductor ...
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... Figure 3-15 DRAM Page Mode Read Accesses Freescale Semiconductor 131 137 139 140 141 Column Column Address Address 143 133 153 Data In Data In DSP56362 Technical Data, Rev. 4 External Memory Expansion Port (Port A) 136 135 138 142 Last Column Address 132 152 134 154 Data In AA0474 3-27 ...
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... T t CAC C 1.5 × OFF 1.75 × 3.25 × RAS C 1.75 × RSH C DSP56362 Technical Data, Rev. 4 Chip Frequency (MHz) AA0475 MHz 30 MHz Min Max Min Max 250.0 — 166.7 C − 7.5 — 130.0 — 84.2 − 7.5 — ...
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... DS C 1.75 × 3.25 × DHR C 3 × T − 4.3 t WCS C 0.5 × CSR C 1.25 × RPC C DSP56362 Technical Data, Rev. 4 External Memory Expansion Port (Port (continued MHz 30 MHz Min Max Min Max − 4.0 133.5 — 87.7 − 4.0 58.5 — 37.7 ± 2 73.0 77.0 48.0 52.0 ± ...
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... RC t RAC t CAC OFF RAS t RSH t CSH t CAS t RCD t RAD t CRP ASR DSP56362 Technical Data, Rev (continued MHz 30 MHz Min Max Min Max − 4.0 221.0 — 146.0 — 192.5 — 125.8 0.0 — 0.0 − 0.3 37.2 — 24.7 — 12.5 — C and not t ...
Page 57
... The number of wait states for out-of-page access is specified in the DCR. 2 The refresh period is specified in the DCR deassertion will always occur after CAS deassertion; therefore, the restricted timing The asynchronous delays specified in the expressions are valid for DSP56362. 5 Either must be satisfied for read cycles. RCH ...
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... ASC 5.25 × CAH 7.75 × RAL t RCS 1.75 × RCH 0.25 × RRH 0.25 × WCH t WCR DSP56362 Technical Data, Rev 100 MHz 4 Expression Unit Min Max 12 × T 120.0 — − 7.0 — 55 − 7.0 — 30 4.5 × T − ...
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... The number of wait states for out-of-page access is specified in the DCR. 2 The refresh period is specified in the DCR deassertion will always occur after CAS deassertion; therefore, the restricted timing The asynchronous delays specified in the expressions are valid for DSP56362. 5 Either must be satisfied for read cycles. RCH ...
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... WCH C 9.5 × T − 4.2 t WCR C 15.5 × 15.75 × RWL C 14.25 × CWL C 8.75 × DSP56362 Technical Data, Rev (continued) 100 MHz 120 MHz Min Max Min Max 0.0 — 0.0 — − 4.0 58.5 — 48.1 — − 4.0 93.5 — 77.2 — − 4.0 58.5 — ...
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... CSR C 4.75 × RPC C 15.5 × ROH C 14 × T − 5 0.75 × 0.25 × T DSP56362 Technical Data, Rev. 4 External Memory Expansion Port (Port (continued) 100 MHz 120 MHz Min Max Min Max − 4.0 58.5 — 48.1 — − 4.0 93.5 — 77.2 — 90.7 — ...
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... Figure 3-17 DRAM Out-of-Page Read Access 3-36 157 163 165 167 164 168 170 166 171 173 175 Row Address Column Address 172 176 177 191 160 159 158 192 DSP56362 Technical Data, Rev. 4 162 174 179 168 193 161 Data In AA0476 Freescale Semiconductor ...
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... Row Address Column Address 181 175 188 180 182 184 183 187 186 185 194 Data Out DSP56362 Technical Data, Rev. 4 External Memory Expansion Port (Port A) 162 174 195 AA0477 3-37 ...
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... Data in valid to CLKOUT high (setup) 207 CLKOUT high to data in invalid (hold) 208 CLKOUT high to RD assertion 3-38 157 163 162 165 189 Figure 3-19 DRAM Refresh Access 4 4 DSP56362 Technical Data, Rev. 4 162 AA0478 1 100 MHz , 2 3 Expression Min Max 0.25 × 4.0 — 6.5 C 0.25 × ...
Page 65
... WS is the number of wait states specified in the BCR. 3 The asynchronous delays specified in the expressions are valid for DSP56362. 4 T198 and T199 are valid for Address Trace mode if the ATE bit in the OMR is set. Use the status of BR (See T212) to determine whether the access referenced by A0–A23 is internal or external, when this mode is enabled > ...
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... External Memory Expansion Port (Port A) CLKOUT A0–A17 AA0–AA3 TA WR D0–D23 RD D0–D23 Figure 3-20 Synchronous Bus Timings SRAM 1 WS (BCR Controlled) 3-40 198 210 203 Data Out 202 208 206 DSP56362 Technical Data, Rev. 4 199 201 200 211 205 204 209 207 Data In AA0479 Freescale Semiconductor ...
Page 67
... CLKOUT high to BB assertion (input hold) 217 CLKOUT high to BB assertion (output) Freescale Semiconductor 201 200 203 Data Out 202 206 Table 3-18 Arbitration Bus Timings 2 DSP56362 Technical Data, Rev. 4 External Memory Expansion Port (Port A) 199 201 200 211 205 204 209 207 Data In AA0480 ...
Page 68
... CLKOUT high to AA deassertion 224 CLKOUT high to AA high impedance 1 The asynchronous delays specified in the expressions are valid for DSP56362. 2 T212 is valid for Address Trace mode when the ATE bit in the OMR is set deasserted for internal accesses and asserted for external accesses. ...
Page 69
... CLKOUT 212 A0–A17 RD, WR AA0–AA3 Figure 3-23 Bus Release Timings Case 1 (BRT Bit in OMR Cleared) Freescale Semiconductor External Memory Expansion Port (Port A) 214 213 219 218 221 224 223 DSP56362 Technical Data, Rev. 4 AA0482 3-43 ...
Page 70
... In order to guarantee timings 250, and 251 recommended to assert BG inputs to different 56300 devices (on the same bus non overlap manner as shown in 3-44 214 213 221 224 223 Expression 2 . Table 3-19 Figure 3-25 . DSP56362 Technical Data, Rev. 4 219 218 AA0483 100 MHz Unit Min Max — — required ...
Page 71
... BG asserted, and BB negated, may cause another 56300 component to assume mastership at the same time. Therefore some non-overlap period between one BG input active to another BG input active, is required. Timing 251 ensures that such a situation is avoided. Freescale Semiconductor External Memory Expansion Port (Port A) 250 250+251 DSP56362 Technical Data, Rev. 4 251 3-45 ...
Page 72
... HCS assertion to output data valid 3-46 3 Expression 4 4 2.5 × after “Last Data Register” HACK write assertion width 8 2.5 × DSP56362 Technical Data, Rev 100 MHz Min Max T + 9.9 19.9 — C — 9.9 — + 6.6 31.6 — C — 13.2 — + 6.6 31.6 — C 16.5 — ...
Page 73
... Delay from DMA HACK assertion to HOREQ deassertion for “Last Data Register” read or write • HROD = 1, open drain Host Request 1 See Host Port Usage Considerations in the DSP56362 User Design Manual the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable 3.3 V ± ...
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... HRD, HDS HD0–HD7 HOREQ, HRRQ, HTRQ Figure 3-28 Read Timing Diagram, Non-Multiplexed Bus 3-48 317 327 329 326 336 337 333 330 317 318 328 332 319 327 329 326 340 341 DSP56362 Technical Data, Rev. 4 318 328 AA1105 338 AA0484 Freescale Semiconductor ...
Page 75
... HA0–HA2 HCS HWR, HDS HD0–HD7 HOREQ, HRRQ, HTRQ Figure 3-29 Write Timing Diagram, Non-Multiplexed Bus Freescale Semiconductor 336 331 320 321 324 340 341 DSP56362 Technical Data, Rev. 4 Parallel Host Interface (HDI08) Timing 337 333 325 339 AA0485 3-49 ...
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... HA8–HA10 322 HAS HRD, HDS HAD0–HAD7 HOREQ, HRRQ, HTRQ Figure 3-30 Read Timing Diagram, Multiplexed Bus 3-50 336 337 323 317 334 335 327 328 329 Address Data 326 340 341 DSP56362 Technical Data, Rev. 4 318 319 338 AA0486 Freescale Semiconductor ...
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... Figure 3-32 Host DMA Write Timing Diagram Freescale Semiconductor 336 323 320 334 324 335 Data Address 340 341 342 343 344 320 321 TXH/M/L Write 324 325 Data Valid DSP56362 Technical Data, Rev. 4 Parallel Host Interface (HDI08) Timing 321 325 339 AA0487 3-51 ...
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... Master Bypassed SPICC Narrow Wide Master Bypassed Narrow Wide Slave Bypassed Narrow Wide Master Bypassed Narrow Wide Slave Bypassed Narrow Wide DSP56362 Technical Data, Rev. 4 342 318 328 329 100MHz Expression Min Max — — 0 — 50 — 100 6×T +46 106 — C 6× ...
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... Slave — Master/ Bypassed Slave Narrow Wide Master/ Bypassed Slave Narrow Wide Slave — Slave Bypassed Narrow Wide Slave Bypassed Narrow Wide DSP56362 Technical Data, Rev. 4 100MHz Expression Unit Min Max — — 10 — — 2000 3.5×T +15 50 — — — ...
Page 80
... Wide Master — Master — 143 142 144 142 144 143 148 149 MSB Valid 152 MSB 163 Figure 3-34 SPI Master Timing (CPHA = 0) DSP56362 Technical Data, Rev. 4 100MHz Expression Min Max 2.5×T +30 55 — — C 0.5 × 121 — SPICC 2.5× ...
Page 81
... Freescale Semiconductor 143 142 144 142 144 143 148 149 MSB Valid 152 MSB 162 163 Figure 3-35 SPI Slave Timing (CPHA = 0) DSP56362 Technical Data, Rev. 4 Serial Host Interface SPI Protocol Timing 141 144 141 144 148 149 LSB Valid 153 LSB AA0272 3-55 ...
Page 82
... MOSI (Output) 161 HREQ (Input) 3-56 143 142 144 142 144 143 148 149 MSB Valid 152 MSB 162 163 Figure 3-36 SPI Master Timing (CPHA = 1) DSP56362 Technical Data, Rev. 4 141 144 141 144 148 149 LSB Valid 153 LSB AA0272 Freescale Semiconductor ...
Page 83
... MSB 148 149 MSB Valid 157 Figure 3-37 SPI Slave Timing (CPHA = 0) DSP56362 Technical Data, Rev. 4 Serial Host Interface SPI Protocol Timing 141 147 144 160 141 144 151 LSB 149 LSB Valid 159 AA0273 ...
Page 84
... MOSI (Input) HREQ (Output) 3-58 143 144 142 144 143 152 MSB 148 149 MSB Valid 157 Figure 3-38 SPI Slave Timing (CPHA = 1) DSP56362 Technical Data, Rev. 4 141 147 144 144 153 151 LSB 148 149 LSB Valid 158 AA0274 Freescale Semiconductor ...
Page 85
... F DSP 10.6 11.8 13.1 t 0.0 SU;RQI T NG;RQO × — C × 120 — C × 208 — C DSP56362 Technical Data, Rev Protocol Timing Fast-Mode Unit Max Min Max 0 — — 50 100 — 100 100 — 400 — 1.3 — — 0.6 — — 0.6 — ...
Page 86
... T if HDM and HRS $ C × HDM and HRS $ C ), SCL rise time (T I2CCP R Table 3-23 DSP56362 Technical Data, Rev. 4 Standard Fast-Mode Max Min Max — 50 — — 100 — — 155 — — 927 — — 882 — — ...
Page 87
... MSB LSB 186 182 189 184 2 Figure 3- Timing DSP56362 Technical Data, Rev Serial Host Interface (SHI Protocol Timing + 45ns + 135ns + 223ns + environment = 8930ns – ...
Page 88
... T C — — — — 6 — — 6 — — — — — — — — — — 6 — — — — DSP56362 Technical Data, Rev. 4 100 MHz Condition Min Max 40.0 — — [3xT ; 454 10.0 — 15.0 — 10.0 — ...
Page 89
... T C 21.0 — 7 — — — — — — DSP56362 Technical Data, Rev. 4 Enhanced Serial Audio Interface Timing 100 MHz 4 Condition Unit Min Max 3.0 — 0.0 — 0.0 — 19.0 — ...
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... Periodically sampled and not 100% tested. 3- Symbol Expression — — — — — — — — — — — — — — — — DSP56362 Technical Data, Rev. 4 100 MHz 4 Condition Unit Min Max — 27.0 — ns — 31.0 — ns 2.0 — 21.0 — 4.0 — ...
Page 91
... In normal mode, the output flag state is asserted for the entire frame period. Freescale Semiconductor 430 432 446 447 450 454 454 452 First Bit 459 453 461 458 461 460 462 Figure 3-40 ESAI Transmitter Timing DSP56362 Technical Data, Rev. 4 Enhanced Serial Audio Interface Timing 451 455 Last Bit 456 See Note AA0490 3-65 ...
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... FSR (Word) In Flags In HCKT SCKT(output) 3-66 430 431 432 433 434 437 439 First Bit 441 443 442 444 Figure 3-41 ESAI Receiver Timing 463 464 Figure 3-42 ESAI HCKT Timing DSP56362 Technical Data, Rev. 4 438 440 Last Bit 443 445 AA0491 Freescale Semiconductor ...
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... ACI low duration 223 ACI rising edge to ADO valid 1 In order to assure proper operation of the DAX, the ACI frequency should be less than 1/2 of the DSP56362 internal clock frequency. For example, if the DSP56362 is running at 100 MHz internally, the ACI frequency should be less than 50 MHz. ACI ...
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... Figure 3-45 TIO Timer Event Input Restrictions CLKOUT TIO (Input) Address 3-68 Table 3-26 Timer Timing = 480 481 482 483 First Interrupt Instruction Execution Figure 3-46 Timer Interrupt Generation DSP56362 Technical Data, Rev 100 MHz Expression Min Max 2 × 2.0 22.0 — × 2.0 22.0 — ...
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... GPIO out fall time 3.3 V ± 0. 0°C to +100° Freescale Semiconductor 484 Figure 3-47 External Pulse Generation Table 3-27 GPIO Timing Expression 6.75 × DSP56362 Technical Data, Rev. 4 GPIO Timing 485 AA0494 1 100 MHz Min Max — 31.0 3.0 — 12.0 — 0.0 — ...
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... TCK low to output data valid 507 TCK low to output high impedance 3-70 492 493 Valid 494 495 496 Figure 3-48 GPIO Timing Table 3-28 JTAG Timing Characteristics × 3); maximum 22 MHz) C DSP56362 Technical Data, Rev. 4 490 491 AA0495 1, 2 All Frequencies Min Max 0.0 22.0 45.0 — 20.0 — 0.0 3 ...
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... All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. V TCK (Input) 503 Figure 3-49 Test Clock Input Timing Diagram Freescale Semiconductor 1, 2 Table 3-28 JTAG Timing (continued) Characteristics = 501 502 DSP56362 Technical Data, Rev. 4 JTAG Timing All Frequencies Min Max 5.0 — 25.0 — 0.0 44.0 0.0 44.0 100.0 — 40.0 — 502 V M ...
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... Figure 3-51 Test Access Port Timing Diagram 3-72 504 Input Data Valid 506 Output Data Valid 507 506 Output Data Valid 508 Input Data Valid 510 Output Data Valid 511 510 Output Data Valid DSP56362 Technical Data, Rev. 4 VIH 505 AA0497 VIH 509 AA0498 Freescale Semiconductor ...
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... O CE Module TimIng n No. Characteristics 500 TCK frequency of operation 514 DE assertion time in order to enter Debug mode 515 Response time when DSP56362 is executing NOP instructions from internal memory 516 Debug acknowledge assertion time 3.3 V ± 0. 0°C to +100° 514 ...
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... OnCE Module TimIng 3-74 NOTES DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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... Pin-out and Package Information This section provides information about the available package for this product, including diagrams of the package pinouts and tables describing how the signals described in Descriptions” are allocated for the package. The DSP56362 is available in a 144-pin LQFP package. 4.2 LQFP Package Description ...
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... Note: Because of size constraints in this figure, only one name is shown for multiplexed pins. Refer to Table 4-2 and for detailed information about pin functions and signal names. Figure 4-1 DSP56362 Thin Quad Flat Pack (LQFP), Top View 4-2 (Top View) DSP56362 DSP56362 Technical Data, Rev. 4 ...
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... Table 4-1 DSP56362 LQFP Signal Identification by Pin Number 1 Pin No. Signal Name 1 SCK/SCL 2 SS/HA2 3 HREQ 4 SDO0 or PC11 5 SDO1 or PC10 6 SDO2/SDI3 or PC9 7 SDO3/SDI2 or PC8 8 V CCS 9 GND S 10 SDO4/SDI1 or PC7 11 SDO5/SDI0 or PC6 12 FST or PC4 13 FSR or PC1 14 SCKT or PC3 15 SCKR or PC0 16 HCKT or PC5 17 HCKR or PC2 ...
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... LQFP Package Description Table 4-1 DSP56362 LQFP Signal Identification by Pin Number (continued) 1 Pin No. Signal Name CCA 81 GND CCA 87 GND A 88 A10 89 A11 90 GND CCQL 92 A12 93 A13 94 A14 95 V CCQH 96 GND A 97 ...
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... Table 4-2 DSP56362 LQFP Signal Identification by Name Signal Name Pin No. not connected A10 88 A11 89 A12 92 A13 93 A14 94 A15 97 A16 98 A17 AA0 70 AA1 69 AA2 51 AA3 50 ACI 28 ADO Freescale Semiconductor Signal Name Pin No ...
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... LQFP Package Description Table 4-2 DSP56362 LQFP Signal Identification by Name (continued) Signal Name Pin No CAS 52 CLKOUT 59 D0 100 D1 101 D10 114 D11 115 D12 116 HOREQ/HOREQ 24 HRD/HRD 22 HREQ 3 HRRQ/HRRQ 23 HRW 22 HCKR 17 HCKT 16 HTRQ/HTRQ 24 HWR/HWR 21 IRQA 137 IRQB 136 IRQC 135 IRQD ...
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... Table 4-2 DSP56362 LQFP Signal Identification by Name (continued) Signal Name Pin No. NMI 61 PB0 43 PB1 42 PB10 31 PB11 22 PB12 21 PB13 30 PB14 24 PB15 23 PB2 41 PB3 40 PB4 37 PB5 36 PB6 35 PB7 34 PB8 33 Freescale Semiconductor Signal Name Pin No. RAS2 52 RAS3 RESET 44 SCK 1 SCKR 15 SCKT 14 SCL 1 SDA 144 ...
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... LQFP Package Mechanical Drawing 4.3 LQFP PACKAGE MECHANICAL DRAWING Figure 4-2 DSP56362 144-pin LQFP Package 4-8 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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... Freescale Semiconductor , in °C can be obtained from the following equation × θ θJA θJC θCA . For example, the user can change the air flow around θCA θJA DSP56362 Technical Data, Rev not satisfactorily answer whether 5-1 ...
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... IRQB, IRQC, IRQD, TA, and BG pins. Maximum PCB trace lengths on the order inches) are recommended. 5 determined by a thermocouple, the thermal resistance T CAUTION ). The suggested value for a pullup or pulldown resistor CC power source to GND. CC DSP56362 Technical Data, Rev has been defined JT pin on the DSP and from CC and GND. CC Freescale Semiconductor and CC ...
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... Take special care to minimize noise levels on the V • If multiple DSP56362 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. • RESET must be asserted when the chip is powered up. A stable EXTAL signal should be supplied before deassertion of RESET. • ...
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... MHz and MF ≤ 4, this jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this jitter is less than ±2 ns. 5 1MHz = – I typF2 typF1 NOTE DSP56362 Technical Data, Rev. 4 × – Freescale Semiconductor ...
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... Exercise care when reading status bits HF3 and HF2 as an encoded pair. If the DSP changes HF3 and HF2 from 00 to 11, there is a small probability that the host could read the bits during the transition and receive instead of 11. If the combination of HF3 and HF2 has Freescale Semiconductor DSP56362 Technical Data, Rev. 4 Host Port Considerations 5-5 ...
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... HF0 and HF1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have significance). A very small probability exists that the DSP will read the status bits synchronized during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus. 5-6 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
Page 115
... Ordering Information Consult a Freescale Semiconductor, Inc. sales office or authorized distributor to determine product availability and to place an order. For information on ordering this and all DSP Audio products, review the SG1004 selector guide at http://www.freescale.com. Freescale Semiconductor DSP56362 Technical Data, Rev. 4 6-1 ...
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... NOTES DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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... Interrupt vectors for program debug only ; MAIN (external) program starting address ; INTERNAL X-data memory starting address ; INTERNAL Y-data memory starting address P:START #$0d0000,x:M_PCTL ; PLL enable ; CLKOUT disable #INT_PROG,r0 #PROG_START,r1 #(PROG_END-PROG_START),PLOAD_LOOP p:(r1)+,x0 x0,p:(r0)+ #INT_XDAT,r0 #XDAT_START,r1 DSP56362 Technical Data, Rev XTAL disable A-1 ...
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... PROG_END nop nop XDAT_START ; org A-2 #(XDAT_END-XDAT_START),XLOAD_LOOP p:(r1)+,x0 x0,x:(r0)+ #INT_YDAT,r0 #YDAT_START,r1 #(YDAT_END-YDAT_START),YLOAD_LOOP p:(r1)+,x0 x0,y:(r0)+ INT_PROG #$0,r0 #$0,r4 #$3f,m0 #$3f, #$0,x0 #$0,x1 #$0,y0 #$0,y1 #4,omr ; ebd #60,_end x0,y0,a x:(r0)+,x1 x1,y1,a x:(r0)+,x0 a,b x0,y0,a x:(r0)+,x1 x1,y1,a b1,x:$ff sbr x:0 $262EB9 $86F2FE $E56A5F $616CAC DSP56362 Technical Data, Rev. 4 y:(r4)+,y1 y:(r4)+,y0 y:(r4)+,y0 Freescale Semiconductor ...
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... DSP56362 Technical Data, Rev. 4 A-3 ...
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... DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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... YDAT_END Freescale Semiconductor $4B3E8C $6079D5 $E0F5EA $8230DB $A3B778 $2BFE51 $E0A6B6 $68FFB7 $28F324 $8F2E8D $667842 $83E053 $A1FD90 $6B2689 $85B68E $622EAF $6162BC $E4A245 DSP56362 Technical Data, Rev. 4 A-5 ...
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... A-6 NOTES DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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... DSP56362 Technical Data, Rev. 4 max 75m 4.3nH 1.4pF B-1 ...
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... DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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... DSP56362 Technical Data, Rev. 4 B-3 ...
Page 126
... I/O 5.00pF 5.00pF 3.3v 3v 3.6v I(min) I(max) -3.65e+02 -5.18e+02 -3.30e+02 -4.67e+02 -2.94e+02 -4.16e+02 -2.59e+02 -3.65e+02 -2.23e+02 -3.14e+02 -1.88e+02 -2.63e+02 -1.52e+02 -2.12e+02 -1.17e+02 -1.61e+02 -9.25e+01 -1.10e+02 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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... I(min) I(max) 2.177e-04 4.123e-04 2.175e-04 4.021e-04 2.173e-04 3.946e-04 2.172e-04 3.893e-04 2.171e-04 3.857e-04 2.170e-04 3.834e-04 2.169e-04 3.820e-04 2.167e-04 3.812e-04 2.520e-04 3.808e-04 DSP56362 Technical Data, Rev. 4 B-5 ...
Page 128
... I(min) I(max) -3.65e+02 -5.18e+02 -3.30e+02 -4.67e+02 -2.94e+02 -4.16e+02 -2.59e+02 -3.65e+02 -2.23e+02 -3.14e+02 -1.88e+02 -2.63e+02 -1.52e+02 -2.12e+02 -1.17e+02 -1.61e+02 -9.25e+01 -1.10e+02 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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... DSP56362 Technical Data, Rev. 4 1.320/0.366 1.520/0.431 B-7 ...
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... DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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... I(min) I(max) DSP56362 Technical Data, Rev. 4 B-9 ...
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... DSP56362 Technical Data, Rev. 4 1.320/0.366 1.520/0.431 Freescale Semiconductor ...
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... DSP56362 Technical Data, Rev. 4 B-11 ...
Page 134
... I(min) I(max) 1.905e+02 2.686e+02 1.725e+02 2.428e+02 1.545e+02 2.170e+02 1.365e+02 1.912e+02 1.185e+02 1.655e+02 1.005e+02 1.397e+02 8.253e+01 1.139e+02 6.454e+01 8.814e+01 5.068e+01 6.237e+01 3.859e+01 4.389e+01 2.651e+01 2.662e+01 1.444e+01 9.359e+00 2.517e+00 3.554e-02 1.577e-02 9.211e-04 7.857e-05 1.655e-05 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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... DSP56362 Technical Data, Rev. 4 1.900/0.124 1.880/0.155 B-13 ...
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... DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
Page 137
... I(min) I(max) 1.905e+02 2.686e+02 1.725e+02 2.428e+02 1.545e+02 2.170e+02 1.365e+02 1.912e+02 1.185e+02 1.655e+02 1.005e+02 1.397e+02 8.253e+01 1.139e+02 6.454e+01 8.814e+01 DSP56362 Technical Data, Rev. 4 B-15 ...
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... DSP56362 Technical Data, Rev. 4 1.900/0.124 1.880/0.155 Freescale Semiconductor ...
Page 139
... DSP56362 Technical Data, Rev. 4 B-17 ...
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... I(min) I(max) 1.896e+02 2.677e+02 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
Page 141
... Input 5.00pF 5.00pF 3.3v 3v 3.6v I(min) I(max) -3.65e+02 -5.17e+02 -3.29e+02 -4.66e+02 -2.94e+02 -4.15e+02 -2.58e+02 -3.64e+02 -2.23e+02 -3.13e+02 -1.88e+02 -2.62e+02 -1.52e+02 -2.11e+02 -1.17e+02 -1.60e+02 -9.24e+01 -1.10e+02 -6.87e+01 -7.57e+01 -4.51e+01 -4.16e+01 -2.15e+01 -7.64e+00 -1.16e+00 -4.87e-03 -4.39e-03 -3.03e-04 DSP56362 Technical Data, Rev. 4 1.810/0.149 1.800/0.205 B-19 ...
Page 142
... I/O 5.00pF 5.00pF 3.3v 3v 3.6v I(min) I(max) -3.65e+02 -5.17e+02 -3.29e+02 -4.66e+02 -2.94e+02 -4.15e+02 -2.58e+02 -3.64e+02 -2.23e+02 -3.13e+02 -1.88e+02 -2.62e+02 -1.52e+02 -2.11e+02 -1.17e+02 -1.60e+02 -9.24e+01 -1.10e+02 -6.87e+01 -7.57e+01 -4.51e+01 -4.17e+01 -2.15e+01 -7.66e+00 -1.17e+00 -3.79e-02 -1.67e-02 -2.81e-02 -9.77e-03 -2.04e-02 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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... I(min) I(max) 1.885e+02 2.667e+02 1.707e+02 2.411e+02 1.528e+02 2.155e+02 1.350e+02 1.898e+02 1.172e+02 1.642e+02 9.935e+01 1.386e+02 8.152e+01 1.130e+02 6.369e+01 8.739e+01 4.999e+01 6.178e+01 3.806e+01 4.346e+01 2.613e+01 2.635e+01 1.421e+01 9.245e+00 2.435e+00 6.260e-02 2.689e-02 3.437e-02 1.265e-02 2.451e-02 DSP56362 Technical Data, Rev. 4 B-21 ...
Page 144
... I(min) I(max) -3.65e+02 -5.17e+02 -3.29e+02 -4.66e+02 -2.94e+02 -4.15e+02 -2.58e+02 -3.64e+02 -2.23e+02 -3.13e+02 -1.88e+02 -2.62e+02 -1.52e+02 -2.11e+02 -1.17e+02 -1.60e+02 -9.24e+01 -1.10e+02 -6.87e+01 -7.57e+01 -4.51e+01 -4.16e+01 -2.15e+01 -7.64e+00 -1.16e+00 -4.87e-03 -4.39e-03 -3.03e-04 -2.55e-05 -2.73e-06 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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... I(min) I(max) 0.699/0.978 0.642/0.956 Input 5.00pF 5.00pF 3.3v 3v 3.6v I(min) I(max) -3.66e+02 -5.18e+02 -3.30e+02 -4.67e+02 -2.95e+02 -4.16e+02 -2.59e+02 -3.65e+02 -2.24e+02 -3.14e+02 -1.89e+02 -2.63e+02 DSP56362 Technical Data, Rev. 4 1.400/0.354 1.350/0.350 B-23 ...
Page 146
... DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
Page 147
... DRAM controller 4 DSP programming 6 E electrical design considerations 3 Enhanced Serial Audio Interface 4 ESAI 4, 2 ESSI receiver timing 66, 67 timings 62 transmitter timing 65 EXTAL jitter 5 external bus control 6, 7 external bus synchronous timings (SRAM access) DSP56362 Technical Data, Rev. 4 Index-1 ...
Page 148
... Wait state 12 J Jitter 5 JTAG 20 JTAG Port 3 reset timing diagram 73 timing 70 maximum ratings 1 Memory Expansion Port 3 mode control 8 Mode select timing 7 multiplexed bus 2 multiplexed bus timings read 50 write 51 N non-multiplexed bus 2 non-multiplexed bus timings read 48 write 49 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
Page 149
... Reset timing 10 T TAP 3 target applications 5 Test Access Port 3 Test Access Port timing diagram 72 Test Clock (TCLK) input timing diagram 71 thermal characteristics 2 thermal design considerations 1 Timer event input restrictions 68 interrupt generation 68 timing 68 Timing Digital Audio Transmitter (DAX) 67 DSP56362 Technical Data, Rev. 4 Index-3 ...
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... Serial Host Interface (SHI) SPI Protocol Tim- ing 52 Serial Host Interface (SHI) Timing 52 timing interrupt 7 mode select 7 Reset 7 Stop 7 TQFP 1 pin list by number 3 pin-out drawing (top Wait mode data RAM data RAM 3 Index-4 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...
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... Freescale Semiconductor DSP56362 Technical Data, Rev. 4 Index-5 ...
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... For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 303-675-2140 DSP56362 Document Number: Rev. 4 08/2006 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...