dsp56852 Freescale Semiconductor, Inc, dsp56852 Datasheet - Page 26

• Manufacturer Part Number: dsp56852
• Description: 56800e 16-bit Digital Signal Controllers Digital Signal Controller
• Manufacturer: Freescale Semiconductor, Inc

4.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Operating Conditions: V
26
RESET Assertion to Address, Data and Control Signals
High Impedance
Minimum RESET Assertion Duration
RESET Deassertion to First External Address Output
Edge-sensitive Interrupt Request Width
IRQA, IRQB Assertion to External Data Memory Access
Out Valid, caused by first instruction execution in the
interrupt service routine
IRQA, IRQB Assertion to General Purpose Output Valid,
caused by first instruction execution in the interrupt
service routine
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State
Delay from IRQA Assertion (exiting Stop) to External
Data Memory
Delay from IRQA Assertion (exiting Wait) to External
Data Memory
RSTO pulse width
normal operation
internal reset mode
1. In the formulas, T = clock cycle. For f
2. Parameters listed are guaranteed by design.
3. At reset, the PLL is disabled and bypassed. The part is then put into run mode and t
t
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not
the minimum required so that the IRQA interrupt is accepted.
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
6. Fast stop mode:
(OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes one less cycle
and t
7. Normal stop mode:
recovery will take an extra cycle (to restart the clock), and t
8. ET = External Clock period, For an external crystal frequency of 8MHz, ET=125 ns.
extal
Fast
Normal
As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master clock,
Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is requested
or t
clk
6
will continue same value it had before stop mode was entered.
osc
7
.
5
Table 4-8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
8
SS
Characteristic
= V
4
SSIO
= V
SSA
= 0V, V
3
op
= 120MHz operation and f
DD
= 1.62-1.98V, V
56852 Technical Data, Rev. 8
clk
will resume at the input clock source rate.
DDIO
t
Symbol
t
IDM -FAST
t
IRI -FAST
IG -FAST
t
t
RSTO
t
t
t
ipb
RAZ
t
RDA
t
IRW
IDM
t
t
t
RA
IRI
IW
IG
IF
= V
= 60MHz, T = 8.33ns.
DDA
= 3.0–3.6V, T
128ET
1T + 3
22ET
1.5T
8ET
18T
14T
18T
14T
22T
18T
18T
Min
30
—
—
clk
assumes the period of the source clock, t
A
120T
Max
= –40° to +120°C, C
11
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
Freescale Semiconductor
L
1, 2
< 50pF, f
See Figure
4-11
4-11
4-11
4-12
4-13
4-13
4-14
4-15
4-15
4-16
op
= 120MHz
xtal
,