dsp56824 Freescale Semiconductor, Inc, dsp56824 Datasheet - Page 43

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dsp56824

Manufacturer Part Number
dsp56824
Description
16-bit Digital Signal Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
No.
142
143
144
145
146
147
148
149
1.
2.
inverted frame sync (FSI = 0 in CRB). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal SCK and/or the frame sync FSR/FST in the tables and in
the figures.
3.
The following abbreviations are used to represent the various operational cases:
i ck = Internal Clock and Frame Sync
x ck = External Clock and Frame Sync
i ck s = Internal Clock, Synchronous mode (implies that only one frame sync FS is used)
x ck s = External Clock, Synchronous mode (implies that only one frame sync FS is used)
All the timings for the SSI are given for a non-inverted serial clock polarity (SCKP = 0 in CRB) and a non-
bl = bit length; wl = word length.
STCK high to STD enable from high impedance
STCK high to STD valid
STCK high to STD not valid
STCK high to STD high impedance
SRD setup before STCK falling
SRD hold after STCK falling
SRD setup before STCK falling
SRD hold after STCK falling
Freescale Semiconductor, Inc.
(in addition to standard external clock parameters)
(in addition to standard internal clock parameters)
For More Information On This Product,
Table 29. SSI Timing (Continued)
Characteristic
Synchronous External Clock Operation
Synchronous Internal Clock Operation
4
4
DSP56824 Technical Data
Go to: www.freescale.com
Synchronous Serial Interface (SSI) Timing
11.7
18.4
–4.7
Min
7.8
5.8
9.2
1.7
0
70 MHz
Max
28.5
21.1
22.9
19
Case
x ck s
x ck s
i ck s
i ck s
x ck
x ck
x ck
x ck
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
43

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