saa7118 NXP Semiconductors, saa7118 Datasheet - Page 71

• Manufacturer Part Number: saa7118
• Description: Multistandard Video Decoder With Adaptive Comb Filter And Component Video Input
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 15219
Product data sheet
9.2 Audio clock signals
9.3 Clock and real-time synchronization signals
The SAA7118 also synchronizes the audio clock and sampling rate to the video frame
rate, via a very slow PLL. This ensures that the multimedia capture and compression
processes always gather the same predefined number of samples per video frame.
An audio master clock AMCLK and two divided clocks ASCLK and ALRCLK are
generated:
The ratios are programmable; see
Table 26:
[1]
For the generation of the line-locked video (pixel) clock LLC, and of the frame-locked
audio serial bit clock, a crystal accurate frequency reference is required. An oscillator is
built-in for fundamental or third harmonic crystals. The supported crystal frequencies are
32.11 MHz or 24.576 MHz (defined during reset by strapping pin ALRCLK).
Alternatively pin XTALI can be driven from an external single-ended oscillator.
The crystal oscillation can be propagated as a clock to other ICs in the system via
pin XTOUT.
The Line-Locked Clock (LLC) is the double pixel clock of nominal 27 MHz. It is locked to
the selected video input, generating baseband video pixels according to “ITU
recommendation 601” . In order to support interfacing circuits, a direct pixel clock (LLC2) is
also provided.
Symbol
AMCLK
AMXCLK M12
ASCLK
ALRCLK
•
•
ASCLK: can be used as audio serial clock
ALRCLK: audio left/right channel clock
Pin numbers for QFP160 in parenthesis.
Pin
P11
(72)
(76)
N11
(74)
P12
(75)
Audio clock pin description
[1]
I/O Description
O
I
O
O
Rev. 06 — 22 December 2005
audio master clock output
external audio master clock
input for the clock division
circuit, can be directly
connected to output
AMCLK for standard
applications
serial audio clock output,
can be synchronized to
rising or falling edge of
AMXCLK
audio channel (left/right)
clock output, can be
synchronized to rising or
falling edge of ASCLK
Multistandard video decoder with adaptive comb filter
Section
8.7.
Bit
ACPF[17:0] 32h[1:0] 31h[7:0] 30h[7:0] and
ACNI[21:0] 36h[5:0] 35h[7:0] 34h[7:0]
SDIV[5:0] 38h[5:0] and SCPH[3Ah[0]]
LRDIV[5:0] 39h[5:0] and LRPH[3Ah[1]]
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SAA7118
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