at40kel040 ATMEL Corporation, at40kel040 Datasheet - Page 27

• Manufacturer Part Number: at40kel040
• Description: Rad Hard Reprogrammable Fpgas With Freeram
• Manufacturer: ATMEL Corporation

AC Timing
Characteristics
Clocks and Reset Input buffers are measured from a V
Maximum timings for clock input buffers and internal drivers are measured for rising edge delays only.
Notes:
4155I–AERO–06/06
Cell Function
Global Clocks and Set/Reset
GCK Input buffer
FCK Input buffer
Clock column driver
Clock sector driver
GSRN Input buffer
Global clock to output
Fast clock to output
1. CMOS buffer delays are measured from a V
2. Buffer delay is to a pad voltage of 1.5V with one output switching.
3. Parameter based on characterization and simulation; not tested in production.
4. Exact power calculation is available in Atmel FPGA Designer software.
Parameter
t
t
t
t
t
t
t
PD
PD
PD
PD
PD
PD
PD
(max)
(max)
(max)
(max)
(max)
(max)
(max)
Path
pad -> clock
pad -> clock
clock -> colclk
colclk -> secclk
colclk -> secclk
clock pad -> out
clock pad -> out
IH
of 1/2 V
IH
of 1.5V at the input pad to the internal V
CC
at the pad to the internal V
Value
10.3
21.3
19.9
3.3
1.9
1.7
0.8
Unit
ns
ns
ns
ns
ns
ns
ns
IH
at A. The input buffer load is constant.
Notes
rising edge clock
rising edge clock
rising edge clock
rising edge clock
rising edge clock
fully loaded clock tree
rising edge DFF
20 mA output buffer
50 pf pin load
rising edge clock
fully loaded clock tree
rising edge DFF
20 mA output buffer
50 pf pin load
IH
of 50% of V
CC
.
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