xc4020e-xl Xilinx Corp., xc4020e-xl Datasheet - Page 46

• Manufacturer Part Number: xc4020e-xl
• Description: Xc4000e And Xc4000x Series Field Programmable Gate Arrays
• Manufacturer: Xilinx Corp.

XC4000E and XC4000X Series Field Programmable Gate Arrays
used), and if RAM is present, the RAM content must be
unchanged.
Statistically, one error out of 2048 might go undetected.
Configuration Sequence
There are four major steps in the XC4000 Series power-up
configuration sequence.
• Configuration Memory Clear
• Initialization
• Configuration
• Start-Up
The full process is illustrated in
Configuration Memory Clear
When power is first applied or is reapplied to an FPGA, an
internal circuit forces initialization of the configuration logic.
When Vcc reaches an operational level, and the circuit
passes the write and read test of a sample pair of configu-
ration bits, a time delay is started. This time delay is nomi-
nally 16 ms, and up to 10% longer in the low-voltage
devices. The delay is four times as long when in Master
Modes (M0 Low), to allow ample time for all slaves to reach
a stable Vcc. When all INIT pins are tied together, as rec-
ommended, the longest delay takes precedence. There-
fore, devices with different time delays can easily be mixed
and matched in a daisy chain.
This delay is applied only on power-up. It is not applied
when re-configuring an FPGA by pulsing the PROGRAM
pin
6-50
Figure 45: Circuit for Generating CRC-16
0
1
LAST DATA FRAME
X2
1
1
1
2 3 4 5 6 7 8 9 10 11 12 13 14
1
1 0 15 14 13 12 11 10 9 8 7 6 5
Polynomial: X16 + X15 + X2 + 1
Readback Data Stream
CRC – CHECKSUM
Figure
SERIAL DATA IN
46.
X15
X1789
15
X16
SAMPLE PRELOAD
Figure 46: Power-up Configuration Sequence
(* if PROGRAM = High)
SAMPLE/PRELOAD
SAMPLE/PRELOAD
Boundary Scan
CONFIGURE
CONFIGURE*
READBACK
Instructions
Available:
EXTEST*
BYPASS
BYPASS
BYPASS
EXTEST
USER 1
USER 2
Master CCLK
Goes Active
If Boundary Scan
is Selected
F
Configuration Memory
Configuration Memory
One Time-Out Pulse
Test M0 Generate
Completely Clear
Data to DOUT
of 16 or 64 ms
Keep Clearing
Configuration
Configuration
Count Equals
Data Frame
Operational
Mode Lines
Once More
Yes
Yes
Yes
Load One
Sequence
No
Start-Up
memory
High? if
Sample
Master
Config-
Length
>3.5 V
Frame
uration
CCLK
Count
Error
Pass
V
INIT
Full
CC
Yes
Yes
May 14, 1999 (Version 1.6)
No
No
No
No
Master Waits 50 to 250 s
Before Sampling Mode Lines
~1.3 s per Frame
Pull INIT Low
and Stop
PROGRAM
= Low
Yes
X6076
R