at94k40al ATMEL Corporation, at94k40al Datasheet - Page 74

• Manufacturer Part Number: at94k40al
• Description: At94kal Series Field Programmable System Level Integrated Circuit
• Manufacturer: ATMEL Corporation

4.18.3.1
4.18.4
4.18.5
74
AT94KAL Series FPSLIC
Using the Boundary-scan Chain
Using the On-chip Debug System
TAP Controller
The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-
Scan circuitry and On-Chip Debug system. The state transitions depicted in
on the signal present on TMS (shown adjacent to each state transition) at the time of the rising
edge at TCK. The initial state after a Power-On Reset is Test-Logic-Reset.
As a definition in this document, the LSB is shifted in and out first for all shift registers.
Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is
As shown in
selecting JTAG instruction and using Data Registers, and some JTAG instructions may select
certain functions to be performed in the Run-Test/Idle, making it unsuitable as an Idle state.
Note:
A complete description of the Boundary-Scan capabilities are given in the section
(JTAG) Boundary-scan” on page
As shown in
All read or modify/write operations needed for implementing the Debugger are done by applying
AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O
memory mapped location which is part of the communication interface between the CPU and the
JTAG system.
• At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched
• At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data
• A scan chain on the interface between the internal AVR CPU and the internal peripheral units
• A breakpoint unit
• A communication interface between the CPU and JTAG system
• A scan chain on the interface between the internal AVR CPU and the FPGA
• A scan chain on the interface between the internal Program/Data SRAM and the FPGA
Instruction Register - Shift-IR state. While TMS is Low, shift the 4 bit JTAG instructions into
the JTAG instruction register from the TDI input at the rising edge of TCK, while the captured
IR-state 0x01 is shifts out on the TDO pin. The JTAG Instruction selects a particular Data
Register as path between TDI and TDO and controls the circuitry surrounding the selected
Data Register.
onto the parallel output from the shift register path in the Update-IR state. The Exit-IR, Pause-
IR, and Exit2-IR states are only used for navigating the state machine.
Data Register - Shift-DR state. While TMS is Low, upload the selected Data Register
(selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input
at the rising edge of TCK. At the same time, the parallel inputs to the Data Register captured
in the Capture-DR state shifts out on the TDO pin.
Register has a latched parallel-output, the latching takes place in the Update-DR state. The
Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine.
1. Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be
entered by holding TMS High for 5 TCK clock periods.
Figure
Figure 4-17 on page
4-16, the hardware support for On-Chip Debugging consists mainly of
76.
73, the Run-Test/Idle
(1)
state need not be entered between
Figure 4-17
“IEEE 1149.1
1138I–FPSLI–1/08
depend