mpc8343e Freescale Semiconductor, Inc, mpc8343e Datasheet - Page 41

• Manufacturer Part Number: mpc8343e
• Description: Mpc8343e Powerquicc
• Manufacturer: Freescale Semiconductor, Inc

Figure 26
Figure 27
Freescale Semiconductor
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device (including
hysteresis)
Noise margin at the HIGH level for each connected device (including
hysteresis)
Notes:
1. The symbols for timing specifications follow the pattern of t
2. MPC8343E provides a hold time of at least 300 ns for the SDA signal (referred to the V
3. The maximum t
4. C
and t
respect to the time data input signals (D) reach the valid state (V) relative to the t
state or setup time. Also, t
goes invalid (X) relative to the t
timing (I2) for the time that the data with respect to the stop condition (P) reaches the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
the undefined region of the falling edge of SCL.
B
SDA
SCL
= capacitance of one bus line in pF.
(first two letters of functional block)(reference)(state)(signal)(state)
provides the AC test load for the I
shows the AC timing diagram for the I
MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11
S
I2DVKH
t
I2CF
t
I2CL
t
I2SXKL
must be met only if the device does not stretch the LOW period (t
Output
I2SXKL
Parameter
Table 35. I
I2C
symbolizes I
clock reference (K) going to the low (L) state or hold time. Also, t
Figure 27. I
t
I2DXKL
2
C AC Electrical Specifications (continued)
Figure 26. I
2
t
Z
C timing (I2) for the time that the data with respect to the start condition (S)
I2DVKH
0
= 50 Ω
t
2
I2CH
2
C.
C Bus AC Timing Diagram
2
t
I2SXKL
2
C bus.
C AC Test Load
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
Sr
t
I2SVKH
Symbol
R
t
t
t
I2KHKL
I2KHDX
I2PVKH
t
t
V
L
V
I2CR
I2CF
NH
NL
= 50 Ω
I2C
1
clock reference (K) going to the high (H)
I2DVKH
20 + 0.1 C
20 + 0.1 C
0.1 × OV
0.2 × OV
t
IH
I2PVKH
OV
I2CL
(min) of the SCL signal) to bridge
Min
0.6
1.3
DD
) of the SCL signal.
symbolizes I
t
I2CR
/2
DD
DD
b
b
4
4
I2PVKH
P
Max
2
t
300
300
I2CF
—
—
—
—
C timing (I2) with
symbolizes I
S
for inputs
I2C
Unit
ns
ns
μs
μs
clock
V
V
2
C
I
41
2
C