adv202 Analog Devices, Inc., adv202 Datasheet - Page 13

• Manufacturer Part Number: adv202
• Description: Jpeg2000 Video Codec
• Manufacturer: Analog Devices, Inc.

EXTERNAL DMA MODE—FIFO WRITE, BURST MODE
Table 8.
Parameter
DREQ
t
t
t
t
WE
WE
t
1
2
3
DREQ RTN
DACK SU
SU
HD
DREQ WAIT
Applies to assigned DMA channel, if EDMOD0 or EDMOD1[14:11] is programmed to a value that is not 0. Pulse width depends on the value programmed.
For a definition of JCLK, see the PLL section.
If sufficient space is available in FIFO.
LO
HI
PULSE
HDATA
HDATA
DREQ
DACK
DREQ
DACK
WE
WE
Description
DREQ Pulse Width
WE to DREQ Deassert (DR × Pulse = 0)
DACK to WE Setup
Data Setup
Data Hold
WE Assert Pulse Width
WE Deassert Pulse Width
Last Burst Access to Next DREQ
1
DREQ
Figure 13. Burst Write Cycle for DREQ /DMA Mode for Assigned DMA Channel
Figure 14. Burst Write Cycle for DREQ /DMA Mode for Assigned DMA Channel
t
t
PULSE
t
(EDMOD0/EDMOD1[14:11] NOT Programmed to a Value of 0000)
t
SU
SU
DACKSU
DACKSU
0
0
(EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000)
t
t
HD
HD
t
DREQRTN
1
1
Rev. C | Page 13 of 40
WE
WE
LO
LO
13
13
Min
1
2.5
0
2.5
2
1.5
1.5
2.5
14
14
Typ
WE
WE
HI
HI
Max
15
3.5 × JCLK + 7.5 ns
4.5 × JCLK + 7.5 ns
15
15
t
t
DREQWAIT
DREQWAIT
3
Unit
JCLK
JCLK cycles
ns
ns
ns
JCLK cycles
JCLK cycles
JCLK cycles
ADV202
2
cycles