mc33902 Freescale Semiconductor, Inc, mc33902 Datasheet - Page 18

• Manufacturer Part Number: mc33902
• Description: High Speed Can Interface With Embedded 5.0 V Supply
• Manufacturer: Freescale Semiconductor, Inc

Termination
terminations:
• Differential termination resistors between CANH and
• Split termination concept, with the mid point of the differen-
• Refer to
.
Wake-up
enabled, the CAN bus traffic is detected. The CAN bus wake-
up signal is a pattern wake-up. CAN wake-up cannot be
disabled.
CAN Wake-up Report
selected, Sleep or Standby. In Sleep mode, the INH pin is
activated. In Standby mode, the VIO voltage is present and
the wake-up is reported by the ERR and RXD pin low level.
Ref to
.
18
33902
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The device supports the two main types of bus
CANL lines
tial termination connected to GND through a capacitor,
and to the SPLIT pin
and WAKE Pin Configuration on page 27
When the CAN interface is in Sleep mode with wake-up
The CAN wake reports depend upon the low power mode
Table
SPLIT
2.5 V
Typical Application and Bus Termination Options
2.5 V
CANL
CANH
5.
TXD
RXD
Internal differential wake-up
receiver signal
MC33902: bus driver
Internal wake-up signal
Dominant state
CANH-DOM
CANL-DOM
CANH-CANL
CAN bus
Normal or Listen Only mode
Recessive state
CANL/CANH-REC
Figure 12. Bus Signal in Normal and Low Power Mode
min
Dominant
Pulse # 1
t
PWIDTH
(bus dominant set by other IC)
CANH
MC33902: receiver
CANL
Figure 13. Pattern Wake-up
max 120 μs
Incoming CAN Message
Dominant
Pulse # 2
Low Power Mode
VSUP pin.
disabled, and the receiver is also disabled. CANH and CANL
have a typical 40 kΩ impedance to GND. The wake-up
receiver can be activated if wake-up is enabled by the P_SPI
command. The SPLIT pin is high-impedance.
CANL are set back into the recessive level. This is illustrated
in the following diagram.
Pattern Wake-up
receiver must receive a series of 3 consecutive valid
dominant pulses. This is the default setting in which the CAN
WU-pattern bit is set low. CAN WU-pattern bit can be set high
by P_SPI, and the wake up will occur after a single pulse
duration of a minimum of 4.0 μs.
3 pulses should occur in a time frame of 120 μs to be
considered valid. When 3 pulses pass these criteria the wake
signal is detected. This is illustrated in
In low power mode, the CAN is internally supplied from the
In low power mode, the CANH and CANL drivers are
When the device is set back into Normal mode, CANH and
In order to wake-up the CAN interface, the wake-up
A valid dominant pulse should be longer than t
Dominant
Pulse # 3
High ohmic t termination (50kohms) to GND
Sleep or Standby mode
Go to Sleep,
High-impedance
Analog Integrated Circuit Device Data
Dominant
Pulse # 4
Freescale Semiconductor
Normal or Listen Only mode
Figure
13.
PWIDTH
. The