mc33561dtbr2 ETC-unknow, mc33561dtbr2 Datasheet - Page 3

• Manufacturer Part Number: mc33561dtbr2
• Description: Power Management Interface Smartcard Readers Couplers
• Manufacturer: ETC-unknow

CONTROLLER INTERFACE
CARD INTERFACE
Pin
12
13
14
15
16
17
2
3
4
5
6
7
8
9
PWR_ON
RDY_MOD
CS
RESET
I/O
SYN_CLK
ASY_CLK_IN
INT
CRD_IO
CRD_GND
CRD_VCC
CRD_RST
CRD_CLK
CRD_DET
Symbol
INPUT
Pull Down
I/O and Pull Up
INPUT
Pull Up
INPUT
Pull Down
Input/Output
CLOCK INPUT
Pull Down
CLOCK INPUT
High Impedance
OUTPUT
Pull Down
I/O
GROUND
POWER
OUTPUT
OUTPUT
INPUT
Type
Table 1. Pin Functions and Description
This pin valid the operation of the internal DC/DC converter.
This bidirectional pin features tri–state output and schmitt trigger input. When
RDY_MOD is forced to 0, the MC33xxx is set to programming mode by a negative
transition on CS pin.
This pin provides the MC33561 chip select function. Pins x x x are disabled when
CS = H. When RDY_MOD = L, the device jumps in the programming mode upon
the falling edge of CS (See Figure YY).
The signal presents as this pin is translated to pin XX (card reset signal) when
CS = L. The signal on this pin is latched when CS = H. This pin is also used in
programming mode (See ZZZ).
This pin is connected to an external microcontroller interface. A bidirectional level
translator adapts the serial I/O signal between the smartcard and the
microcontroller. The level translator is enabled when CS = L. The signal present on
this pin is latched when CS = H. This pin is also used in programming mode
(See ZZZ).
This pin, generally connected to the controller serial interface clock, is used to set
up communications with synchronous cards. The signal is fed to the internal clock
selector circuit and is translated to CRD_CLK upon appropriate programming of the
MC33561. When the device operates in the programming mode, the signal presents
on this pin is latched when CS = H.
This pin can be connected to either the microcontroller master clock, or to any clock
signal, to drive the asynchronous cards. The signal is fed to internal clock selector
circuit and translated to the CRD_CLK at either the same frequency, or divided by 2
or 4, depending upon the programming mode (See AAA).
This pin is activated LOW when a card has been inserted and detected by the
interface. The signal is reset to a logic 1 on the rising edge of either CS or
PWR_ON. The Collector open mode makes possible the wired AND/OR external
logic. When two or more interfaces share the INT function with a single micro
controller, the software must polls the MC33561 to identify the origin of the interupt.
This pin handles the connection to the serial I/O pin of the card connector. A
bi–directional level translator adapts the serial I/O signal between the card and the
micro controller.
This pin is connected to the external card ground. It is the ground reference for all
analog and digital signals.
This pin provides the power to the external card. It is the logic level “1” for CRD_IO,
CRD_RST and CRD_CLK signals.
This pin is connected to the RESET pin of the card connector. A level translator
adapts the RESET signal from the micro controller to the external card.
This pin is connected to the CLK pin of the card connector. The CRD_CLK signal
comes from the clock selector circuit output. The clock selection is programmed by
using pins x x x with RDY_MOD forced to a logic zero.
The signal coming from the external card connector is used to detect the presence
of the card. A built in pull up resistor makes this pin active LOW.
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MC33561
3
Name/Function