cp2200 Silicon Laboratories, cp2200 Datasheet - Page 84

• Manufacturer Part Number: cp2200
• Description: Single-chip Ethernet Controller
• Manufacturer: Silicon Laboratories

CP2200/1
84
Bits 15–7:Reserved. Read = 000000000b; Must write 000000000b.
Bits 6–0: IPGT: Back-to-Back Inter-Packet Gap Register
Bit 15:
Bits 14–8:IPGR1: Non-Back-to-Back Inter-Packet Gap Part 1
Bit 7:
Bits 6–0: IPGR2: Non-Back-to-Back Inter-Packet Gap Part 2
Reserved
Reserved
Reserved
Bit15
Bit15
R/W
R/W
R/W
R/W
Bit7
Bit7
Indirect Register 4. IPGR: Non-Back-to-Back Inter-Packet Gap Register
Sets the minimum delay between the end of any transmitted packet and the start of a new packet.
In Full-Duplex mode, the register value should be set to the desired number of time units (each time
unit is 0.46 µs) minus 3. The recommended setting is 0x15 (21d), which yields 9.6 µs.
In Half-Duplex mode, the register value should be set to the desired number of time units (each time
unit is 0.46 µs) minus 6. The recommended setting is 0x12 (18d), which yields 9.6 µs.
Reserved. Read = 0b; Must write 0b.
Sets the optional carrier sense window referenced in IEEE 802.3 Section 4.2.3.2.1. The range of
values for this bit field are 0x00 to IPGR2. The recommended value is 0x0C.
Reserved. Read = 0b; Must write 0b.
Sets the Non-Back-to-Back Inter-Packet Gap. The recommended value is 0x12, which represents a
minimum inter-packet gap of 9.6 µs.
Indirect Register 3. IPGT: Back-to-Back Inter-Packet Gap Register
Bit14
Bit14
R/W
R/W
R/W
R/W
Bit6
Bit6
Bit13
Bit13
R/W
R/W
R/W
R/W
Bit5
Bit5
Bit12
Bit12
R/W
R/W
R/W
R/W
Bit4
Bit4
Reserved
IPGR1
IPGR2
IPGT
Bit11
Bit11
R/W
R/W
R/W
R/W
Bit3
Bit3
Rev. 1.0
Bit10
Bit10
R/W
R/W
R/W
R/W
Bit2
Bit2
R/W
R/W
R/W
R/W
Bit9
Bit1
Bit9
Bit1
R/W
R/W
R/W
R/W
Bit8
Bit0
Bit8
Bit0
Default Value
Default Value
MACADDR:
MACADDR:
0x0000
0x0000
0x02
0x03