adm6995 ETC-unknow, adm6995 Datasheet - Page 19

• Manufacturer Part Number: adm6995
• Description: Port 10/100 Mb/s Single Chip Ethiernet Switch Controller
• Manufacturer: ETC-unknow

ADM6995L
ADMtek Inc.
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
All digital design is especial immune from noise environments and achieves better
correlation between production and system testing. Baud rate Adaptive Equalizer/Timing
Recovery compensates line loss induced from twisted pair and tracks far end clock at
125M samples per second. Adaptive Equalizer implemented with Feed forward and
Decision Feedback techniques meet the requirement of BER less than 10-12 for
transmission on CAT5 twisted pair cable ranging from 0 to 120 meters.
The recovered data is converted from NRZI to NRZ. The data is not necessarily aligned
to 4B/5B code group’s boundary.
The de-scrambler acquires synchronization with the data stream by recognizing idle
bursts of 40 or more bits and locking its deciphering Linear Feedback Shift Register
(LFSR) to the state of the scrambling LFSR. Upon achieving synchronization, the
incoming data is XORed by the deciphering LFSR and de-scrambled.
In order to maintain synchronization, the de-scrambler continuously monitors the validity
of the unscrambled data that it generates. To ensure this, a link state monitor and a hold
timer are used to constantly monitor the synchronization status. Upon synchronization of
the de-scrambler the hold timer starts a 722 us countdown. Upon detection of sufficient
idle symbols within the 722 us period, the hold timer will reset and begin a new
countdown. This monitoring operation will continue indefinitely given a properly
operating network connection with good signal integrity. If the link state monitor does
not recognize sufficient unscrambled idle symbols within 722 us period, the de-scrambler
will be forced out of the current state of synchronization and reset in order to re-acquire
synchronization.
The symbol alignment circuit in the ADM6995L determines code word alignment by
recognizing the /J/K delimiter pair. This circuit operates on unaligned data from the de-
scrambler. Once the /J/K symbol pair (11000 10001) is detected, subsequent data is
aligned on a fixed boundary.
The symbol decoder functions as a look-up table that translates incoming 5B symbols
into 4B nibbles as shown in Table 1. The symbol decoder first detects the /J/K symbol
pair preceded by idle symbols and replaces the symbol with MAC preamble. All
subsequent 5B symbols are converted to the corresponding 4B nibbles for the duration of
the entire packet. This conversion ceases upon the detection of the /T/R symbol pair
Adaptive Equalizer and timing Recovery Module
NRZI/NRZ and Serial/Parallel Decoder
Data De-scrambling
Symbol Alignment
Symbol Decoding
Function Description
3-3