saf-xc866-4rri3v Infineon Technologies Corporation, saf-xc866-4rri3v Datasheet - Page 108
saf-xc866-4rri3v
Manufacturer Part Number
saf-xc866-4rri3v
Description
8-bit Single-chip Microcontroller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.SAF-XC866-4RRI3V.pdf
(116 pages)
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4.3.3
Table 42
Parameter
Pad operating voltage
On-Chip Oscillator
start-up time
Flash initialization time
RESET hold time
PLL lock-in in time
PLL accumulated jitter
1)
2)
Figure 42
Data Sheet
Flash State
RESET signal has to be active (low) until
PLL lock at 80 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 40 and P = 1.
RESET
VDDC
VDDP
OSC
PLL
Pads
t
RST
Power-on Reset and PLL Timing
1)
I)until EVR is stable
Power-on Reset Timing
2)
V
Power-On Reset and PLL Timing (Operating Conditions apply)
PAD
1)
1)Pad state undefined
t
OSCST
V
t
t
t
t
D
Symbol
OSCST
FINIT
RST
LOCK
Reset
PAD
P
II)until PLL is locked
CC
CC –
SR
CC –
CC 2.3
PLL unlock
V
DDC
t
LOCK
–
min. typ.
–
–
2)ENPS control 3)As Programmed
has reached 90% of its maximum value (typ. 2.5V).
Limit Values
104
–
–
160
500
–
–
3)
to Ready-to-Read
III) until Flash go
Initialization
t
max.
–
500
–
–
200
0.7
FINIT
V
ns
µs
µs
µs
ns
Unit Test Conditions
IV) CPU reset is released; Boot
ROM software begin execution
PLL lock
V
(10% – 90%) ≤ 500µs
2)
Electrical Parameters
Ready to Read
DDP
rise time
V1.2, 2007-10
XC866
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