74vcx162838 Fairchild Semiconductor, 74vcx162838 Datasheet

74vcx162838

Manufacturer Part Number

74vcx162838

Description

Low Voltage 16-bit Selectable Register/buffer With 3.6v Tolerant Inputs And Outputs And 26 ?series Resistors In The Outputs

Manufacturer

Fairchild Semiconductor

Datasheet

1.74VCX162838.pdf (7 pages)

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74VCX162838MTD

74VCX162838

Low Voltage 16-Bit Selectable Register/Buffer

with 3.6V Tolerant Inputs and Outputs

and 26 Series Resistors in the Outputs

General Description

The VCX162838 contains sixteen non-inverting selectable

buffered or registered paths. The device can be configured

to operate in a registered, or flow through buffer mode by

utilizing the register enable (REGE) and Clock (CP) sig-

nals. The device operates in a 16-bit word wide mode. All

outputs can be placed into 3-State through the use of the

OE pin. These devices are ideally suited for buffered or

registered 168 pin and 200 pin SDRAM DIMM memory

modules.

The 74VCX162838 is designed for low voltage (1.65V to

3.6V) V

The VCX162838 is also designed with 26 series resistors

in the outputs. This design reduces line noise in applica-

tions such as memory address drivers, clock drivers, and

bus transceivers/transmitters.

The 74VCX162838 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Ordering Code

applications with I/O compatibility up to 3.6V.

Package Number

MTD48

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS500045

Features

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V

value of the resistor is determined by the current -sourcing capability of the

driver.

Pin Descriptions

Pin Names

REGE

Compatible with PC100 and PC133 DIMM module

specifications

1.65V–3.6V V

3.6V tolerant inputs and outputs

26 series resistors in the outputs

Power-off high impedance inputs and outputs

Supports live insertion and withdrawal (Note 1)

Static Drive (I

Uses patented noise/EMI reduction circuitry

Latch-up performance exceeds 300 mA

ESD performance:

–I

–O

3.9 ns max for 3.0V to 3.6V V

5.4 ns max for 2.3V to 2.7V V

9.8 ns max for 1.65V to 1.95V V

Human body model

Machine model

12 mA @ 3.0V V

8 mA @ 2.3V V

3 mA @ 1.65V V

(CP to O

Package Descriptions

)

Output Enable Input (Active LOW)

Inputs

Outputs

Clock Pulse Input

supply operation

)

200V

through a pull-up resistor. The minimum

2000V

August 1997

Revised July 2000

Description

www.fairchildsemi.com

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74vcx162838 Summary of contents

Page 1

... OE pin. These devices are ideally suited for buffered or registered 168 pin and 200 pin SDRAM DIMM memory modules. The 74VCX162838 is designed for low voltage (1.65V to 3.6V) V applications with I/O compatibility up to 3.6V. CC The VCX162838 is also designed with 26 series resistors in the outputs ...

Page 2

... Immaterial (HIGH or LOW, inputs may not float) Z High Impedance Functional Description The 74VCX162838 consists of sixteen selectable non- inverting buffers or registers with word wide controls. Mode functionality is selected through operation of the CP and REGE pin as shown by the truth table. When REGE is held at a logic “1” the device operates as a 16-bit register. Data ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 3) 0. Input Diode Current ( Output ...

Page 4

DC Electrical Characteristics (2.3V Symbol Parameter V HIGH Level Input Voltage IH V LOW Level Input Voltage IL V HIGH Level Output Voltage OH V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ ...

Page 5

AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX Prop Delay (REGE 0) PHL PLH Prop Delay (REGE 1) PHL PLH ...

Page 6

AC Loading and Waveforms TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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