sta015t STMicroelectronics, sta015t Datasheet - Page 18

• Manufacturer Part Number: sta015t
• Description: Mpeg 2.5 Layer Iii Audio Decoder With Adpcm Capability
• Manufacturer: STMicroelectronics

STA015-STA015B-STA015T
MUTE
Address: 0x14 (20)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
X = don’t care; 0 = normal operation; 1 = mute
The MUTE command is handled according to the
state of the decoder, as described in section 2.5.
MUTE sets the clock running.
DATA_REQ_ENABLE
Address: 0x18 (24)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
The DATA_REQ_ENABLE register is used to
configure Pin n. 28 working as buffered output
clock or data request signal, used for multimedia
SYNCSTATUS
Address: 0x40 (64)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
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MSB
b7
MSB
MSB
X
b7
b7
X
X
X
b6
X
b6
b6
X
X
X
b5
X
b4
X
b5
b5
X
X
X
b3
X
b4
b4
X
X
X
b2
X
b1
b3
b3
X
X
X
X
LSB
b0
0
1
b2
b2
X
0
1
CMD_INTERRUPT
Address: 0x16 (22)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
X = don’t care;
0 = normal operation;
1 = write into I
The INTERRUPT is used to give STA015 the
command to write into the I2C/Ancillary Data
Buffer (Registers: 0x7E ... 0xB5). Every time the
Master has to extract the new buffer content it
writes into this register, setting it to a non-zero
value.
mode.
The buffered Output Clock has the same fre-
quency than the input clock (XTI)
MSB
b7
SS1
X
b1
b1
X
X
0
0
1
b6
X
LSB
LSB
SS0
b0
b0
X
X
0
1
0
2
b5
X
C/Ancillary Data
b4
X
Research of sync word
Wait for Confirmation
buffered output clock
b3
X
request signal
Synchronised
Description
Description
b2
X
b1
X
LSB
b0
0
1