sta333mlj13tr STMicroelectronics, sta333mlj13tr Datasheet
sta333mlj13tr
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sta333mlj13tr Summary of contents
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Features ■ Wide supply voltage range (4.5-18 V) Ω, ■ Vcc = 18 V ■ 3 power output configurations; 2 channels of ternary PWM ■ PowerSSO-36 ...
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Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA333ML 1 Block diagram Figure 1. Block diagram interface Power control Volume control DDX PLL Protection current/thermal Channel 1A Channel 1B Logic Channel 2A Regulators Channel 2B Bias Block diagram 3/15 ...
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Pin description 2 Pin description Figure 2. Pin connection (Top view) TEST_MODE GND_REG Table 1. Pin description Pin 4/15 1 GND_SUB 2 FMT 3 4 VSS_REG 5 VCC_REG ...
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STA333ML Table 1. Pin description (continued) Pin Type Name I/O OUT1A GND GND_REG Power VDD_REG I ...
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Electrical specifications 3 Electrical specifications 3.1 Thermal data Table 2. Thermal data Symbol R Thermal resistance junction to case (thermal pad) Th(j-case) T Thermal shut-down junction temperature sd T Thermal warning temperature w T Thermal shut-down hysteresis hsd 3.2 Absolute ...
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STA333ML 3.4 Electrical characteristics Table 5. Electrical characteristics ( V,VDD_DIG=3 specified) Symbol Parameter Po Output power BTL Power Pchannel/Nchannel R dsON MOSFET (Total Bridge) Power Pchannel/Nchannel l dss leakage Power Pchannel RdsON gP Matching Power ...
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Electrical specifications Table 5. Electrical characteristics (continued V,VDD_DIG=3 specified) Symbol Parameter X Crosstalk TALK η Peak efficiency, DDX mode Table 6. Functional pin status Pin name PWRDN PWRDN 8/15 = 384 kHz ...
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STA333ML 4 Testing Figure 3. Resistive load Duty cycle = 50% Figure 4. Test circuit Duty cycle=A DTin(A) INA Low current dead time = MAX(DTr,DTf) +Vcc M58 OUTxY INxY M57 gnd High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) ...
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Functional description 5 Functional description 5.1 Serial audio interface protocols 2 Figure Lrclki Bicki Sdi Figure 6. Left justified Lrclki/ Lrclko Biclki/ Biclko Sdatai/ 1 Sdatao 5.2 Fault detect recovery bypass The on-chip STA333ML power output block ...
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STA333ML 5.3 Zero-detect mute enable If this function is enabled, the zero-detect circuit examines each processing channel to see if 2048 consecutive zero value samples (regardless of fs) are received the channel is muted. Functional description 11/15 ...
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Package thermal characteristics 6 Package thermal characteristics A thermal resistance of 25 °C per Watt can be achieved using a ground copper area cm, and using 16 vias, on the PCB (see within the device depends ...
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STA333ML 7 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner ...
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Revision history 8 Revision history Table 7. Document revision history Date 1-Feb-2007 14/15 Revision 1 Initial release. STA333ML Changes ...
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... STA333ML Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...