qt510 Quantum Research Group, qt510 Datasheet - Page 6

• Manufacturer Part Number: qt510
• Description: Qwheel? Touch Slider Ic
• Manufacturer: Quantum Research Group

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6.
7.
8.
9.
(Slave Input - MOSI)
(Slave Out - MISO)
prevent cross interference, unless they are
synchronized.
Keep the electrode (and its wiring) away from other
traces carrying AC or switched signals.
If there are LEDs or LED wiring near the electrode or its
wiring (ie for backlighting of the key), bypass the LED
wiring to ground on both the anode and cathode.
Use a voltage regulator just for the QT510 to eliminate
noise coupling from other switching sources via Vdd.
Make sure the regulator’s transient load stability provides
for a stable voltage just before each burst commences.
If Mains noise (50/60 Hz noise) is present, use the Sync
feature to suppress it (see Section 1.1).
Host Data Output
QT Data Output
CLK from Host
DRDY from QT
Acquire Burst
/SS from host
Sleep Mode
<9us delay
edge to data
3-state
?
awake
output driven
<11us after /SS
goes low
?
Data sampled on rising edge
Data shifts out on falling edge
7
7
6
6
response byte
command byte
>13uS, <100uS
>12us, <100us
>12us, <100us
5
5
Figure 3-1 SPI Timing Diagram
4
4
3
3
2
2
1
1
0
0
6
output floats
before DRDY
goes low
3 Serial Communications
The serial interface is a SPI slave-only mode type which is
compatible with multi-drop operation, ie the MISO pin will float
after a shift operation to allow other SPI devices (master or
slave) to talk over the same bus. There should be one
dedicated /SS line for each QT510 from the host controller.
A DRDY (‘data ready’) line is used to indicate to the host
controller when it is possible to talk to the QT510.
3.1 Power-up Timing Delay
Immediately after power-up, DRDY floats for approximately
20ms, then goes low. The device requires ~520ms thereafter
before DRDY goes high again, indicating that the device has
calibrated and is able to communicate.
3.2 SPI Timing
The SPI interface is a five-wire slave-only type; timings are
found in Figure 3-1. The phase clocking is as follows:
The host can shift data to and from the QT on the same cycle
(with overlapping commands). Due to the nature of SPI, the
Data out changes on:
Data Ready DRDY:
<30uS
data hold >=12us
after last clock
Input data read on:
Bit length & order:
low-power sleep; 1s max
3-state
Slave Select /SS:
>35uS
3-state if left to float
Clock rate:
Clock idle:
<1ms, ~920us typ
High
Falling edge of CLK from host
Rising edge of CLK from host
Negative level frame from host
Low from QT inhibits host
8 bits, MSB shifts first
5kHz min, 40kHz max
~31ms
QT510 R6.04/0505
400us typ