x96011 Intersil Corporation, x96011 Datasheet
x96011
Related parts for x96011
x96011 Summary of contents
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... Temperature Sensor with Look Up Table Memory and DAC October 25, 2005 DESCRIPTION The X96011 is a highly integrated bias controller which incorporates a digitally controlled Programmable Cur- rent Generator, and temperature compensation using one look-up table. All functions of the device are con- trolled via a 2-wire digital serial interface. ...
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... Current Generator Output. This pin sinks or sources current. The magnitude and direction of the OUT current is fully programmable and adaptive. The resolution is 8 bits Connect Connect. 11 Vss Ground Connect Connect Connect. 2 X96011 Look-up ADC Table Mux Control & Status 2-Wire Interface Pin Description I DAC Mux OUT October 25, 2005 FN8215.1 ...
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... Temperature Temperature while writing to memory Voltage on Vcc Pin Voltage on any other Pin 3 X96011 COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied ...
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... STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 3. This parameter is periodically sampled and not 100% tested. 4 X96011 Min Typ Max Unit ...
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... The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjust- DAC ing the measured transfer curve for Offset and Full Scale Error expressed in LSB. 3. These parameters are periodically sampled and not 100% tested. 5 X96011 Min Typ Max 1.56 1 ...
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... DNL errors starting from code 00h to the code where the INL measurement is desired. The measured trans- fer curve is adjusted for Offset and Fullscale errors before calculating INL. 3. These parameters are periodically sampled and not 100% tested. 6 X96011 Min Typ Max ...
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... STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 3. The minimum frequency requirement applies between a START and a STOP condition. 4. These parameters are periodically sampled and not 100% tested. 7 X96011 Min Typ Max (3) 1 ...
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... Figure 1. Bus Timing t F SCL t SU:DAT t SU:STA t HD:STA SDA IN SDA OUT Figure 2. WP Pin Timing START SCL SDA IN WP Figure 3. Non-Volatile Write Cycle Timing SCL SDA 8th bit of last byte 8 X96011 HIGH LOW R t HD:DAT Clk SU:WP HD:WP ACK Stop Condition t SU:STO ...
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... The contents of the selected LUT row (8-bit wide) drives the input of an 8-bit D/A converter, which gener- ates the output current. All control and setup parameters of the X96011, including the look-up table, are programmable via the 2-wire serial port. Look Up ...
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... When the NV13 bit is set to “0” (default), bytes written to Control registers 1 and 3 are stored in volatile cells, and their content is lost when the X96011 is powered down. When the NV13 bit is set to “1”, bytes written to Control registers 1 and 3 are stored in both volatile and nonvolatile cells, and their value doesn’ ...
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... Disabled 1: Write Enabled ADC Output 87h AD7 AD6 Volatile Registers in byte addresses 82h, 84h, and 88h through 8Fh are reserved. Registers bits shown should always use these values for proper operation. 11 X96011 NV13 ADCfiltOff 0 0 Control ADC ...
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... When bit LDAS (bit 4 in Control register 5) is set to “1”, the LUT is addressed by these six bits, and it is not addressed by the output of the on-chip A/D converter. When bit LDAS is set to “0”, these six bits are ignored by the X96011. See Figure 7. A value between 00h (00 ) and 3Fh (63 10 ten to these register bits, to select the corresponding row in the LUT ...
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... ATCH OLATILE The WEL bit controls the Write Enable status of the entire X96011 device. This bit must be set to “1” before any other Write operation (volatile or nonvolatile). Oth- erwise, any proceeding Write operation to memory is aborted and no ACK is issued after a Data Byte. ...
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... Figure 5. D/A Converter Block Diagram Internal Reference Voltage Voltage Divider DAC Input byte Figure 6. Look-up Table (LUT) Operation LUT Row Selection bits 90h 14 X96011 Vcc Polarity IDS: bit Select 6 in Control register 0. Circuit + - IFSO[1:0] bits 1 and Control register Vss Vss ...
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... Figure 7. Look-Up Table Addressing Voltage Reference Voltage Input from Internal temperature sensor 15 X96011 D/A Converter Output Current Response When the D/A converter input data byte changes by an arbitrary number of bits, the output current changes from an intial current level (I + ∆ The transition is monotonic and glitchless. ...
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... X96011 ADC TIME POWER-ON RESET When power is applied to the Vcc pin of the X96011, the device undergoes a strict sequence of events before the current outputs of the D/A converters are enabled. When the voltage at Vcc becomes larger than the power-on reset threshold voltage (V recalls all control bits from non-volatile memory into volatile registers ...
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... Data states on the SDA line can change only while SCL is LOW. SDA state changes while SCL is HIGH are reserved for indicating START and STOP condi- tions. See Figure 10. On power-up of the X96011, the SDA pin is in the input mode. Serial Start Condition ...
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... SDA Figure 10. Valid Data Changes on the SDA Bus SCL SDA Figure 11. Acknowledge Response From Receiver SCL from Master SDA Output from Transmitter SDA Output from Receiver START 18 X96011 START Data Stable Data Change 1 STOP Data Stable 8 9 ACK October 25, 2005 FN8215.1 ...
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... Addressing Protocol Overview All Serial Interface operations must begin with a START, followed by a Slave Address Byte. The Slave address selects the X96011, and specifies if a Read or Write operation performed. It should be noted that the Write Enable Latch (WEL) bit must first be set in order to perform a Write opera- tion to any other bit. (See “ ...
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... ACK. The master then terminates the transfer by generating a STOP condition. At this time, if all data bits are volatile, the X96011 is ready for the next read or write operation. If some bits are nonvolatile, the X96011 begins the internal write cycle to the nonvolatile memory ...
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... In both cases the newly written values effectively control the X96011, but in the second case, those val- ues are lost when the part is powered down. If bit NV13 is set to “0”, a Byte Write operation to Con- ...
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... START, the Slave Address byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Slave Address byte with the R/W bit set to “1”. After each of the three bytes, the X96011 responds with an ACK. Then the X96011 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eigth bit of each byte ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 23 X96011 .025 (.65) BSC .169 (4.3) .252 (6.4) BSC ...