qt1106 Quantum Research Group, qt1106 Datasheet - Page 8

• Manufacturer Part Number: qt1106
• Description: Qwheel?/qslide?/qtouch? Ic Touch Screen
• Manufacturer: Quantum Research Group

3 SPI Interface
3.1 Introduction
The QT1106 is an SPI slave mode device. This section
describes the hardware operation of this interface.
3.2 CHANGE Pin
The QT1106 has a CHANGE output pin which allows for key
state change notification. Use of the CHANGE signal relieves
the host of the burden of regularly polling the QT1106 to get
key states. CHANGE goes high when there is a change of
state, i.e. when a new key is pressed, or released, or a
movement is detected on the wheel/slider.
CHANGE also goes high after a reset to indicate to the host
that it should do an SPI transfer in order to provide initial
configuration information to the QT1106 (as it does on every
SPI transfer).
CHANGE goes low after the status is read through an SPI
transfer.
3.3 SPI Parameters
The SPI transmission parameters are:
Lq
•
•
•
•
•
•
•
•
70kHz max clock rate
8 data bits
6.7µs min low clock period
6.7µs min high clock period
Three bytes per transmission, byte 1 most significant
bit sent first
Clock idle high
Shift out on falling edge
Shift in on rising edge
(QT1106 Input - MOSI)
(QT1106 Out - MISO)
Host Data Output
SCLK from Host
QT Data Output
Acquire Bursts
DRDY from QT
/SS pulse during 20us grace period
DRDY from QT
/SS from host
/SS from host
don't care
>450us
3-state
(grace period)
<20us
?
Data sampled on rising edge
7
7 6 5 4 3 2 1 0
<470us
Data shifts out on falling
<17us
6
>22us
>6.7us
>6.7us
Command Byte 1
Response Byte 1
5
4
3 2 1
Figure 3.1 SPI Operation
0
don't care
/SS may go high between
bytes; QT1106 ignores this
7 6
7
8
6
Command Byte 2
Response Byte 2
The host must always transfer three bytes in succession
within the allotted time (10ms maximum). If all bytes are not
received in this interval it is treated by the QT1106 as an
error and the DRDY line will go low before the transmission is
completed.
Messages from the host to the QT1106 carry configuration
information; return data from the QT1106 carries key state
information. For details of the message contents see
Sections 3.5 and 3.6.
3.4 SPI Operation
The basic timing diagram for SPI operation is shown in
Figure 3.1 The host does the clocking and controls the timing
of the transfers, subject to Data Ready (DRDY), from the
QT1106. Transfers are always clocked as a set of three
bytes, Byte 1, 2 and 3.
The host should not attempt to clock the SPI bus to the
device while DRDY is low; during DRDY low the QT1106 is
busy and will ignore SPI activity, with the exception of a 20µs
grace period after the fall of DRDY, where there are no
communications during the high period of DRDY.
Note: DRDY can only become active (go high) if /SS is held
high when idle.
DRDY stays high for at least 450µs. It falls again after Byte 3
has shifted to indicate completion. After the fall of DRDY, the
device acquires (bursts). DRDY goes high to permit SPI
activity after each burst.
After the host asserts /SS low, it should wait >22µs before
starting SCLK. The QT1106 reads the MOSI pin with each
rising edge of SCLK, and shifts data out on the MISO pin on
falling edges. The host should do the same to ensure proper
operation.
Between the end of the Byte 1 shift and the start of the Byte 2
shift (and between Byte 2 and Byte 3), the host may raise
/SS again, but this is not required; the QT1106 ignores /SS
during transfer of the three bytes.
All timings not mentioned above should be as in Figure 3.1.
5
5
<10ms
4 3 2
4
3
2
1
1
0
0
don't care
/SS may go high
between bytes;
QT1106 ignores this
7
7
6
6
Command Byte 3
Response Byte 3
5
5
4
4
>10.8us
3
3
>0us
2
2
1
1
QT1106_8IR0.07_0907
0
0
>0us
~23ms
don't care
>0ns <500ns
3-state
don't care
<5.7us
240ms