hctl-2016-plc Avago Technologies, hctl-2016-plc Datasheet - Page 13

• Manufacturer Part Number: hctl-2016-plc
• Description: Quadrature Decoder/counter Interface Ics
• Manufacturer: Avago Technologies

Actions
1. On the rising edge of the clock,
2. When OE goes low, the
13
counter data is transferred to
the position data latch,
provided the inhibit signal is
low.
outputs of the multiplexer are
enabled onto the data lines. If
SEL is low, then the high order
data bytes are enabled onto the
data lines. If SEL is high, then
the low order data bytes are
enabled onto the data lines.
3. When the IC detects a low on
4. When SEL goes high, the data
5. The first of two reset condi-
OE and SEL during a falling
clock edge, the internal inhibit
signal is activated. This blocks
new data from being
transferred from the counter to
the position data latch.
outputs change from the high
byte to the low byte.
tions for the inhibit logic is
met when the IC detects a
logic high on SEL and a logic
6. When OE goes high, the data
7. The IC detects a logic high on
low on OE during a falling
clock edge.
lines change to a high imped-
ance state.
OE during a falling clock edge.
This satisfies the second reset
condition for the inhibit logic.