adg528abchips Analog Devices, Inc., adg528abchips Datasheet - Page 10

• Manufacturer Part Number: adg528abchips
• Description: Cmos Latched 4/8 Channel Analog Multiplexers
• Manufacturer: Analog Devices, Inc.

ADG528A/ADG529A
TERMINOLOGY
R
R
R
I
I
I
V
C
C
C
t
S
D
D
ON
S
ON
ON
ON
S
D
IN
(OFF)
(OFF)
(ON)
(V
(OFF)
(OFF)
(EN)
Match Difference between the RON of any two channels
Drift
D
)
Ohmic resistance between terminals D and S
Change in RON versus temperature
Source terminal leakage current when the switch
is off.
Drain terminal leakage current when the switch is
off.
Leakage current that flows from the closed switch
into the body.
Analog voltage on terminal S or D
Channel input capacitance for “OFF” condition
Channel output capacitance for “OFF” condition
Digital input capacitance
Delay time between the 50% and 90% points of
the digital input and switch “ON” condition.
0.048 (1.21)
0.042 (1.07)
0.020
(0.50)
R
0.180 (4.57)
0.150 (3.81)
0.110 (2.79)
0.048 (1.21)
0.042 (1.07)
4
8
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
0.395 (10.02)
0.385 (9.78)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
0.356 (9.04)
0.350 (8.89) SQ
MAX
3
(PINS DOWN)
9
TOP VIEW
18-Lead Plastic Dual In-Line Package [PDIP]
20-Lead Plastic Leaded Chip Carrier [PLCC]
0.022 (0.558)
0.014 (0.356)
Dimensions shown in inches and (millimeters)
Dimensions shown in inches and (millimeters)
19
13
COMPLIANT TO JEDEC STANDARDS MO-095AD
SQ
COMPLIANT TO JEDEC STANDARDS MO-047AA
18
1
18
14
0.885 (22.48)
0.845 (21.46)
0.056 (1.42)
0.042 (1.07)
OUTLINE DIMENSIONS
0.050
(1.27)
BSC
0.015 (0.38) MIN
0.100
(2.54)
BSC
0.060 (1.52)
0.045 (1.14)
0.180 (4.57)
0.165 (4.19)
(P-20A)
10
(N-18)
0.120 (3.04)
0.090 (2.29)
9
–10–
t
t
t
V
V
I
V
V
I
I
SEATING
PLANE
OFF
TRANSITION
OPEN
INL
DD
SS
0.295 (7.49)
0.275 (6.99)
INL
INH
DD
SS
0.032 (0.81)
0.026 (0.66)
0.021 (0.53)
0.013 (0.33)
0.20 (0.51)
MIN
0.040 (1.01)
0.025 (0.64)
(I
(EN)
INH
0.325 (8.26)
0.300 (7.62)
)
0.330 (8.38)
0.290 (7.37)
0.015 (0.381)
0.008 (0.203)
R
Delay time between the 50% and 10% points of
the digital input and switch “OFF” condition
Delay time between the 50% and 90% points of
the digital inputs and switch “ON” condition
when switching from one address state to another.
“OFF” time measured between 50% points of
both switches when switching from one address
state to another
Maximum input voltage for Logic “0”
Minimum input voltage for Logic “1”
Input current of the digital input
Most positive voltage supply
Most negative voltage supply
Positive supply current
Negative supply current
0.020 (0.50)
0.180 (4.57)
MAX
R
BOTTOM
(PINS UP)
VIEW
REV. B