adg3241bryz-reel7 Analog Devices, Inc., adg3241bryz-reel7 Datasheet - Page 10

• Manufacturer Part Number: adg3241bryz-reel7
• Description: 2.5 V/3.3 V, 1-bit, 2-port Level Translator Bus Switch In Sot-66
• Manufacturer: Analog Devices, Inc.

ADG3241
TERMINOLOGY
V
Positive power supply voltage.
GND
Ground (0 V) reference.
V
Minimum input voltage for Logic 1.
V
Maximum input voltage for Logic 0.
I
Input leakage current at the control inputs.
I
Off state leakage current. It is the maximum leakage current at
the switch pin in the off state.
I
On state leakage current. It is the maximum leakage current at
the switch pin in the on state.
V
Maximum pass voltage. The maximum pass voltage relates to
the clamped output voltage of an NMOS device when the
switch input voltage is equal to the supply voltage.
R
Ohmic resistance offered by a switch in the on state. It is
measured at a given voltage by forcing a specified amount of
current through the switch.
C
Off switch capacitance.
C
On switch capacitance.
I
OZ
OL
ON
X
X
CC
INH
INL
P
OFF
ON
Rev. B | Page 10 of 16
C
Control input capacitance. This consists of BE and SEL .
I
Quiescent power supply current. This current represents the
leakage current between the V
measured when all control inputs are at a logic high or low level
and the switches are off.
ΔI
Extra power supply current component for the BE control input
when the input is not driven at the supplies.
t
Data propagation delay through the switch in the on state.
Propagation delay is related to the RC time constant R
where C
t
Bus enable times. These are the times taken to cross the V
voltage at the switch output when the switch turns on in
response to the control signal, BE .
t
Bus disable times. These are the times taken to place the switch
in the high impedance off state in response to the control signal.
It is measured as the time taken for the output voltage to change
by V
logic level transition at the control input. Refer to Figure 26 for
enable and disable times.
Max Data Rate
Maximum rate at which data can be passed through the switch.
Channel Jitter
Peak-to-peak value of the sum of the deterministic and random
jitter of the switch channel.
PLH
PZH
PHZ
CC
IN
CC
, t
, t
, t
Δ
PHL
PZL
PLZ
from the original quiescent level, with reference to the
L
is the load capacitance.
CC
and ground pins. It is
ON
× C
T
L
,