tc74vhc123af TOSHIBA Semiconductor CORPORATION, tc74vhc123af Datasheet - Page 6

• Manufacturer Part Number: tc74vhc123af
• Description: Dual Monostable Multivibrator
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Functional Description
(1)
(2)
(3)
(4)
Standby state
triggering, the Q
comparators that relate to the timing of the output pulse, and two reference voltage supplies turn off.
The total supply current is only leakage current.
Trigger operation
input is low, and the B input has a rising signal; second, where the B input is high, and the A input
has a falling signal; and third, where the A input is low and the B input is high, and the CLR
input has a rising signal.
external capacitor discharges through Q
voltage level falls to the internal reference voltage V
then reset and Q
constant of external capacitor C
stays high even if the voltage of R
internal reference voltage V
operation. That means, after triggering, when the voltage level of the R
IC returns to its MONOSTABLE state.
delays of the IC, the width of the output pulse, t
Retrigger operation (TC74VHC123A)
effective only if the IC is charging C
again. Therefore the Q output stays high if the next trigger comes in before the time period set by C
and R
it will have no effect.
Reset operation
the Q output is held low and the trigger control F/F is reset. Also, Q
rapidly to V
The external capacitor (C
Trigger operation is effective in any of the following three cases. First, the condition where the A
After a trigger becomes effective, comparators C
After Q
Upon triggering, output Q becomes high, following some delay time of the internal F/F and gates. It
With large values of C
When a new trigger is applied to either input A or B while in the MONOSTABLE state, it is
If the new trigger is very close to previous trigger, such as an occurrence during the discharge cycle,
The minimum time for a trigger to be effective 2nd trigger, trr (min.), depends on VCC and CX.
In normal operation, the CLR input is held high. If CLR is low, a trigger has no effect because
This means if CLR is set low, the IC goes into a wait state.
X
t
.
w (OUT)
N
turns off, the voltage at the R
CC
.
= 1.0 · C
P
N
and Q
turns off. At that moment C
X
X
N
· R
and R
transistors which are connected to the R
X
ref
) is fully charged to V
X
H, the output of C
X
X
, and ignoring the discharge time of the capacitor and internal
and resistor R
X
/C
X
X
. The voltage level of the R
changes from falling to rising. When R
N
X
. The voltage level at the R
/C
6
X
1
node starts rising at a rate determined by the time
TC74VHC123,221AF/AFN/AFT/AFK
X
w (OUT)
stops but C
2
.
becomes low, the output Q goes low and C
CC
1
and C
ref
in the stand-by state. That means, before
L, the output of C
, is as follows:
2
start operating, and Q
2
continues operating.
X
/C
X
X
P
/C
X
node then falls to V
turns on and C
/C
X
X
X
1
node are in the off state. Two
/C
node drops. If the R
becomes low. The flip-flop is
X
node reaches V
X
/C
X
N
reaches the
is turned on. The
X
is charged
2006-06-01
ref
L level
2
ref
stops its
X
H, the
/C
X
X