w91030b Winbond Electronics Corp America, w91030b Datasheet
w91030b
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w91030b Summary of contents
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... Winbond. Winbond provides this document for reference purposes of W-based system design only. Winbond assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. Preliminary W91030B CALLING LINE IDENTIFIER Publication Release Date: March 2000 ...
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... Bellcore and British Telecom (BT) specifications. There are two types of Caller Identifications, the first type is on-hook calling with caller ID message and the second type is call on waiting. The W91030B device provides all the features and functions of the Caller Identification specification for both these types, including FSK demodulation, Tone Alert Signal detection and ring detection ...
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... FSK Data interface MODE select. Sets the FSK data output interface in mode 0 when low mode 1 when high. 10 OSCI I Oscillator Input. A 3.579545 MHz crystal or ceramic resonator should be connected between this pin and the OSCO pin. May be driven by an external clock source. Preliminary W91030B INP INN 2 ...
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... Dual tone Alert signal Guard time RC (CMOS output and internal voltage comparator input). An external resistor must be connected between this pin and ALGR and an external capacitor between this pin and V implement guard time detection Power supply input. DD Preliminary W91030B DESCRIPTION for normal operation ...
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... The ring signal is detected by the W91030B device and then an interrupt sent to the microcontroller. The ring detected signal will also be directed to the ringer circuit. The data can be decoded by the microcontroller and displayed on the LCD display ...
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... FUNCTIONAL DESCRIPTION Figure 6 is shown functional blocks of W91030B. The device must operate with a 3.579545 MHz system clock and consists four major functions and decribed as follows: Ring Detector The application circuit in Figure 7-1 illustrates the relationship between the RNGDI, RNGRC and RNGON signals. The three pin combination is used to detect an increase of the RNGDI voltage from ground to a level above the Schmitt trigger high going threshold voltage ...
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... The dual tone alert signal is separated into high and low tones and detected by a high/low tone detector. The dual tone alert signal detection circuit is always enabled when the W91030B/BS is not in sleep state. The ALGR is the output of the dual tone detector and when high indicates that the high tone and low tone alert signals have been detected ...
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... Figure 7-4. Guard Time Circuit of Dual Tone Alert Signal Detection Tip/Ring t ALGR ALGRC ALGO Discharge Switch Charge ON Switch Figure 7-5. Guard Time Waveform of ALGR, ALGRC and ALGO pins Preliminary W91030B (the ALGRC pin charges from V SS W91030B Discharge Capacitor Switch Charge/Discharge Control Circuit + - V ...
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... The 3-wire interface, DCLK, DATA and FDRN pins, form the data interface of the FSK demodulation. The DCLK pin is the data clock which is either generated by the W91030B external device. The DATA pin is the serial data pin that outputs data to external devices. The FDRN pin is the data ready signal, also an output from the W91030B to external devices ...
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... Figure 7-7. Serial Data Interface Timing of FSK Demodulation in Mode 0 Mode 1 (MODE = high): The W91030B processes the FSK signal and sets the FDRN pin low to denote the 8-bit boundary and to indicate to the microcontroller that new data has been transmitted. FDRN will return high on the first rising edge of DCLK ...
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... Sleep Mode The W91030B can go into a sleep mode by setting SLEEP high, resulting in reduced power consumption. In this mode, the gain control op-amp, oscillator and all internal circuits, except the ring detector are disabled. The RNGDI, RNGRC and RNGON pins are not affected, so the device can still react to call arrival indicators and activate an interrupt to wake up the microcontroller ...
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... Crystal Oscillator The operation frequency of the W91030B is 3.579545 MHz. Crystal oscillators, ceramic resonators or other clock sources can be used. A crystal oscillator or ceramic resonator can be directly connected to the OSCI and OSCO pins without the need for external components. If other clock sources are used, the OSCI pin should be driven by a clock source and the OSCO pin used to drive other external clocked devices, or left open ...
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... V = 3.0V. The DC electrical characteristics supersede the recommended operating conditions unless otherwise stated PARAMETER CONDITION Operating Supply Voltage Standby Supply Current FSKE = High Operating Supply Current FSKE = Low FSKE = High FSKE = Low Preliminary W91030B SYMBOL (Note SYMBOL RATING V 3 ...
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... C are design aids only, not guaranteed and not subject to production DD testing 0 0 OUT Magnitude measurement, ignore signs. 6. Output - no load. Preliminary W91030B CONDITION SYM. MIN. RNGDI, V 0.48 T+ RNGRC V DD SLEEP 0. 0.2 HYS V 0 FSKE ...
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... These characteristics are for and temperature = Both tones have the same amplitude. Both tones are at the nominal frequencies. 5: Band limited random noise 300 3400 Hz. Present only when the tone is present. Preliminary W91030B SYM. MIN. MAX. UNITS TEST CONDITIONS TYP. ...
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... Note: " " typical figure are and temperature = 25 C are design aids only, not guaranteed and not subject to DD production testing. FSK Detection PARAMETER FSK Detection Enable Time Input FSK to FCDN Low Delay Preliminary W91030B SYMBOL MIN. TYP. F 1188 1200 MARK ...
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... DCLK Low Set-up to FDRN DCLK Low Hold Time After FDRN Note: " " typical figure are and temperature = 25 C are design aids only, not guaranteed and not subject to DD production testing. Preliminary W91030B SYMBOL CONDITION MIN. TYP. FCDN MIN. ...
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... Figure 8-3. FSK Detection Enable and FSK Carrier Detect Present and Absent Timing Note: The minimal delay from FSKE high to FCDN high is t elapsed. DATA DCLK Figure 8-4. Data and DCLK Mode 0 Ouput Timing Preliminary W91030B Figure 8-1. Wake up and Sleep Down Timing Alerting Signal Analog FSK Signal ...
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... DCLK FDRN * Mark bit or redundant stop bit(s), will be omitted. Figure 8-6. Serial Data Interface Timing of FSK Demodulation in Mode 0 DCLK Figure 8-7. DCLK Mode 1 Input Timing Preliminary W91030B 2nd byte data stop start ...
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... Nth byte data Notes: 1. FDRN cleared to high by DCLK. 2. FDRN not cleared, low for maximum time (1/2 bit width). Figure 8-8. Serial Data Interface Timing of FSK Demodulation in Mode 1 Preliminary W91030B (N + 1)th byte data 1/f DCLK1 ...
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... The application circuit of the W91030B in Figure 9-1 shows the device being used within a typical CPE system. Note that only the circuit between the W91030B and the line interface is shown. The gain control op-amp is set to unity gain to allow the electrical characteristics to be met in this application circuit ...
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... Vz - Resistor must have 1% tolerance. Resistor may have 5% tolerance. Crystal is 3.579545MHz with 0.1% frequency tolerance. Figure 9-2. Application Circuit with Improved Common Mode Noise Immunity Microcontroller Interface The following table is the requirement of micorcontroller I/O pin to interface with the W91030B: CASE RNGON SLEEP ...
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... Case 6: If FDRN pin can not monitored by microcontroller and the microcontroller has no interrupt pin to use. In this case, the MODE pin must set low and the W91030B will drive DCLK pin. The microcontroller must track the timing of DCLK pin byte boundary if DCLK high for at least one bit width (1/1200 sec) ...
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... The W91030B may not be woken up at this ring signal after the FSK data has been processed the W91030B has been woken up at the 2nd ring, the microcontroller times out if FCDN is not activated and then puts the W91030B into a sleep condition. ...
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... FSKE may be set low after the last byte (check sum) has been decoded or FCDN has become inactive. 5. For unsuccessful attempts where the end office does not send the FSK signal, the CPE should disable FSKE, unmute the handset and enable the keypad after this interval has elapsed. Preliminary W91030B CPE mutes handset & disables keypad CPE sends ...
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... FSKE pin must always placed in high state and the microcontroller must give up the FSK decoded data when the FSK signal is not expected. 4. The W91030B may not be woken up at this ring signal after the FSK data has been processed. Preliminary W91030B Ch. Seizure Mark ...
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... The FSKE may be set low after the last byte (check sum) has been decoded or FCDN has become inactive unsuccessful attempts where the exchange does not send the FSK signal, the CPE should disable FSKE, unmute the handset and enable the keypad after this interval. Preliminary W91030B CPE mutes handset & disables keypad CPE sends ...
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... TW/P & E/312 specifies that the AC and DC loads should be removed between 50 150 mS after the end of the FSK signal. The W91030B may also be placed in a sleep condition. 4. The W91030B may not be woken up at the first ring cycle after the FSK data had been processed. Preliminary W91030B Ch ...
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... Symbol £ Preliminary W91030B Base Plane A Seating Plane e 1 £\ Dimension in inches Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.210 5.33 0.010 0.25 0.150 0.155 0.160 3.81 3.94 4.06 0.016 ...
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... Package Dimensions, continued 24L SOP-300mil SEATING PLANE Control demensions are in milmeters. SYMBOL Preliminary W91030B Dimension in mm Dimension in Inches MIN. MAX. MIN. MAX. 2.35 0.093 0.104 A 2.65 0.10 0.012 A1 0.30 0.004 0.33 0.51 0.013 0.020 b 0.23 0.32 0.009 0.013 c 7.40 0.291 0.299 E 7.60 15.20 15.60 0.598 0.614 D 1.27 BSC e 0 ...
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... No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. Preliminary W91030B Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U ...