tda4855 NXP Semiconductors, tda4855 Datasheet - Page 7

• Manufacturer Part Number: tda4855
• Description: Autosync Deflection Controller Asdc
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Frequency-locked loop
The frequency-locked loop can lock the horizontal
oscillator over a wide frequency range. This is achieved by
a combined search and PLL operation. The frequency
range is preset by two external resistors and the
recommended maximum ratio is
Larger ranges are possible by extended applications.
Without a horizontal sync signal the oscillator will be
free-running at f
detected by the internal coincidence detector. A deviation
of more than 4% between horizontal sync and oscillator
frequency switches the horizontal section into search
mode. This means that PLL1 control currents are switched
off immediately. Then the internal frequency detector
starts tuning the oscillator. Very small DC currents at
HPLL1 (pin 26) are used to perform this tuning with a well
defined change rate. When coincidence between
horizontal sync and oscillator frequency is detected, the
search mode is replaced by a normal PLL operation.
This operation ensures a smooth tuning and avoids fast
changes of horizontal frequency during catching.
In this concept it is not allowed to load HPLL1.
The frequency dependent voltage at this pin is fed
internally to HBUF (pin 27) via a sample-and-hold and
buffer stage. The sample-and-hold stage removes all
disturbances caused by horizontal sync or composite
vertical sync from the buffered voltage. An external
resistor from HBUF to HREF defines the frequency range.
See also hints for locking procedure in note 3 of
Chapter “Characteristics”.
PLL1 phase detector
The phase detector is a standard type using switched
current sources. It compares the middle of horizontal sync
with a fixed point on the oscillator sawtooth voltage.
The PLL1 loop filter is connected to HPLL1 (pin 26).
Horizontal oscillator
The horizontal oscillator is of the relaxation type and
requires a capacitor of 10 nF at HCAP (pin 29).
For optimum jitter performance the value of 10 nF must not
be changed.
The maximum oscillator frequency is determined by a
resistor from HREF to ground. A resistor from HREF to
HBUF defines the frequency range.
1996 Jul 18
Autosync Deflection Controller (ASDC)
min
. Any change of sync conditions is
---------- -
f
f
max
min
=
------- -
3.5
1
7
The reference current at HREF also defines the integration
time constant of the vertical sync integration.
Calculation of line frequency range
First the oscillator frequencies f
calculated. This is achieved by adding the spread of the
relevant components to the highest and lowest sync
frequencies f
the difference of the currents in R
highest oscillator frequency R
the spread. The spread will increase towards lower
frequencies due to the contribution of R
dependent on the ratio
The following example is a 31.45 to 64 kHz application:
Table 2 Calculation of total spread
Thus the typical frequency range of the oscillator in this
example is:
The resistors R
following formulae:
Where:
n
f
f
R
R
IC
C
R
R
Total
max
min
S
HREF
HBUF
spread of:
HCAP
HREF
HREF
=
=
=
f
------------------ -
f
S max
, R
S min
f
----------------- -
f
=
=
S min
1.087
n
S max
HBUF
74 kHz k
------------------------------------- -
R
-------------------------------------------- -
=
f
HREF
S(min)
max
f
---------- -
f
max
min
=
HREF
=
n 1
---------------------------
31.45 kHz
1.06
kHz
28.93 kHz
and f
–
=
64 kHz
1.19 n
and R
2.35
for f
=
n
S(max)
3%
2%
1%
6%
S
67.84 kHz
HBUF
=
max
=
1.091 k
=
. The oscillator is driven by
=
f
------------------ -
HBUF
f
S max
S min
min
2.26 k
2.04
can be calculated with the
Preliminary specification
HREF
and f
does not contribute to
1%
and R
HBUF
max
TDA4855
(2.3
have to be
for f
8.69%
. It is also
HBUF
3%
2%
min
. At the
n
S
1)