tda4680wp NXP Semiconductors, tda4680wp Datasheet - Page 8

• Manufacturer Part Number: tda4680wp
• Description: Video Processor With Automatic Cut-off And White Level Control
• Manufacturer: NXP Semiconductors

Philips Semiconductors
A
The auto-increment format enables quick slave receiver
initialization by one transmission, when the I
bit BREN = 0 (see control register bits of Table 1).
If BREN = 1 auto-increment is not possible.
If the auto-increment format is selected, the MAD byte is
followed by a SAD byte and by the data bytes of
consecutive sub-addresses (Fig.6).
All sub-addresses from 00H to 0FH are automatically
incremented, the sub-address counter wraps round from
0FH to 00H. Reserved sub-addresses 0BH, 0EH and 0FH
are treated as legal but have no effect. Sub-addresses
outside the range 00H and 0FH are not acknowledged by
the device and neither auto-increment nor any other
internal operation takes place (for versions V1 to V5
sub-addresses outside the range 00H and 0FH are
acknowledged but neither auto-increment nor any other
internal operation takes place).
Sub-addresses are stored in the TDA4680 to address the
following parameters and functions (see Table 1):
The data bytes D7 to D0 (see Table 1) provide the data of
the parameters and functions for video processing.
C
VBWx (Vertical Blanking Window):
The actual lines in the vertical blanking interval after the
start of the vertical pulses selected as measurement lines
for cut-off and white level control are shown in Table 2.
The standards marked with (*) are for progressive line
scan at double line frequency (2f
31 kHz.
NMEN (NTSC Matrix Enable):
1996 Oct 25
UTO
ONTROL REGISTER
Brightness adjust
Saturation adjust
Contrast adjust
Hue control voltage
RGB gain adjust
RGB reference voltage levels
Peak drive limiting adjust
Control register functions.
x = 0, 1 or 2. VBWx selects the vertical blanking interval
and positions the measurement lines for cut-off and
white level control.
0 = PAL/SECAM matrix
1 = NTSC matrix.
Video processor with automatic cut-off
and white level control
-
INCREMENT
1
L
), i.e. approximately
2
C-bus control
8
WPEN (White Pulse Enable):
BREN (Buffer Register Enable):
DELOF (Delay Off) delays the leading edge of clamping
pulses:
SC5 (SandCastle 5 V):
C
FSON2 (Fast Switch 2 ON)
FSDIS2 (Fast Switch 2 Disable)
FSON1 (Fast Switch 1 ON)
FSDIS1 (Fast Switch 1 Disable)
The RGB input signals are selected by FSON2 and
FSON1 or FSW
BCOF (Black level Control Off):
FSBL (Full Screen Black Level):
FSWL (Full Screen White Level):
ONTROL REGISTER
0 = white measuring pulse disabled
1 = white measuring pulse enabled.
0 = new data is executed as soon as it is received
1 = data is stored in buffer registers and is transferred to
the data registers during the next vertical blanking
interval.
The I
until this data is transferred into the data registers.
0 = delay enabled
1 = delay disabled.
0 = 3-level sandcastle pulse
1 = 2-level (5 V) sandcastle pulse.
FSON2 has priority over FSON1
FSW
FSDIS1 and FSDIS2 disable FSW
(see Table 3).
0 = automatic cut-off control enabled
1 = automatic cut-off control disabled; RGB outputs are
clamped to fixed DC levels.
0 = normal mode
1 = full screen black level (cut-off measurement level
during full field).
0 = normal mode
1 = full screen white level (white measurement level
during full field).
2
2
C-bus transceiver does not accept any new data
has priority over FSW
2
and FSW
2
1
:
1
1
Product specification
and FSW
TDA4680
2