m35061-xxxsp Renesas Electronics Corporation., m35061-xxxsp Datasheet - Page 15

• Manufacturer Part Number: m35061-xxxsp
• Description: Screen Character And Pattern Display Controllers
• Manufacturer: Renesas Electronics Corporation.

Notes 1: For internal synchronization, shut out (mute) the external video signal input, outside the IC. This avoids external video signal leaks
14
(9) Address 2B0
DA
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
2: For superimposed color displays, input an fsc signal which is synchronized with the color burst of the composite video signal (input to
3: When EX (address 2B0
4: When using a crystal oscillator (for the fsc input) between the OSCIN and OSCOUT pin, set the SCOR register to “0”.
inside the IC.
the CVIN pin) to the OSCIN pin.
PAL/NTSC
___
DSPONV
SELCOR
INT/NON
16
Register
TEST15
TEST16
DSPON
SEPV0
SEPV1
SCOR
PALH
MPAL
BLK
EX
—
—
____
Status
16
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
) = “1” (internal synchronization), set the SCOR register to “0”.
External synchronization
Internal synchronization
Superimpose black and white display
Superimpose coloring display
Normal
Mode of expansion
Must be cleared to 0.
Digital output display OFF
Digital output display ON
Composite video output display OFF
Composite video output display ON
Must be cleared to 0.
Matrix outline
Matrix outline + border (border color is black)
Test mode (Must be cleared to 0.)
Interlace/noninterlace normal mode
Interlace/noninterlace expansion mode
Interlace
Noninterlace
SEPV1
PAL/NTSC
0
0
1
1
SEPV0
0
0
1
1
0
1
0
1
Separation is performed during 1 in vertical blanking period
Separation is performed during 2 in vertical blanking period
Separation is performed during 3 in vertical blanking period
Setting disabled
MPAL
Composite Sync Spearation Function
0
1
0
1
Contents
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
Function
Setting disabled
Format
M-PAL
NTSC
PAL
M35061-XXXSP/FP
MITSUBISHI MICROCOMPUTERS
(Note 1)
Valid at only register “EX”=0 (at exter-
nal synchronous) (Note 2, 3 and 4)
Refer to Table 3, 4, 7 and 8.
Only at register “DSP1
= 1 (
Method of sync separation from composite video.
Case
within
Valid at only PAL and MPAL
mode.
1
XX
2
condition: vertical sync must repeat 2X
or
= 00 to 16) is valid.
2
3
; indicates this area.
3
Remarks
1
XX
”