74lcx126mx-nl Fairchild Semiconductor, 74lcx126mx-nl Datasheet

74lcx126mx-nl

Manufacturer Part Number

74lcx126mx-nl

Description

74lcx126 Low Voltage Quad Buffer With 5v Tolerant Inputs And Outputs

Manufacturer

Fairchild Semiconductor

Datasheet

1.74LCX126MX-NL.pdf (11 pages)

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74LCX126M

74LCX126SJ

74LCX126BQX

(Note 2)

74LCX126MTC

74LCX126MTCX_NL

(Note 3)

74LCX126

Low Voltage Quad Buffer

with 5V Tolerant Inputs and Outputs

General Description

The LCX126 contains four independent non-inverting buff-

ers with 3-STATE outputs. Each output is disabled when

the associated output-enable (OE) input is LOW. The

inputs tolerate voltages up to 7V allowing the interface of

5V systems to 3V systems.

The 74LCX126 is fabricated with an advanced CMOS tech-

nology to achieve high speed operation while maintaining

CMOS low power dissipation.

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Note 2: DQFN package available in Tape and Reel only.

Note 3: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Please use order number as indicated.

Order Number

MLP014A

Package

Number

MTC14

M14A

M14D

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),

JEDEC MO-241, 2.5 x 3.0mm

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

DS500386

Features

Note 1: To ensure the high-impedance state during power up or down, OE

should be tied to GND through a pull-up resistor: the minimum value or the

resistor is determined by the current-sourcing capability of the driver.

5V tolerant inputs and outputs

2.3V–3.6V V

5.5 ns t

Power down high impedance inputs and outputs

Supports live insertion/withdrawal (Note 1)

Implements patented noise/EMI reduction circuitry

Latch-up performance exceeds JEDEC 78 conditions

ESD performance:

Human body model

Machine model

Leadless Pb-Free DQFN package

24 mA output drive (V

Package Description

max (V

specifications provided

100V

2000V

3.3V), 10

3.0V)

September 2000

Revised May 2005

A I

www.fairchildsemi.com

max

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