dm74als165 Fairchild Semiconductor, dm74als165 Datasheet

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dm74als165

Manufacturer Part Number
dm74als165
Description
8-bit Parallel In/serial Out Shift Register
Manufacturer
Fairchild Semiconductor
Datasheet

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Part Number:
dm74als165MX
Manufacturer:
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Quantity:
20 000
© 2000 Fairchild Semiconductor Corporation
DM74ALS165M
DM74ALS165N
DM74ALS165
8-Bit Parallel In/Serial Out Shift Register
General Description
The DM74ALS165 is an 8-bit serial register that, when
clocked, shifts the data toward serial output, Q
access to each stage is provided by eight individual direct
data inputs that are enabled by a low level at the SH/LD
input. The DM74ALS165 also features a clock inhibit func-
tion and a complemented serial output, Q
Clocking is accomplished by a LOW-to-HIGH transition of
the CLK input while SH/LD is held HIGH and CLK INH is
held LOW. The functions of the CLK and CLK INH (clock
inhibit) inputs are interchangeable. Since a LOW CLK input
and a LOW-to-HIGH transition of CLK INH will also accom-
plish clocking, CLK INH should be changed to the high
level only while the CLK input is HIGH. Parallel loading is
inhibited when SH/LD is held HIGH. The parallel inputs to
the register are enabled while SH/LD is LOW indepen-
dently of the levels of CLK, CLK INH, or SER inputs.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
M16A
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
H
.
H
. Parallel-in
DS006712
Features
Function Table
H
L
X
a...h
Q
Q
Shift/ Clock Clock Serial Parallel
Load Inhibit
A0
An
indicated steady-state input conditions were established
H
H
H
H
H
H
L
Complementary outputs
Direct overriding load (data) inputs
Gated clock inputs
Parallel-to-serial data conversion
LOW Level (steady-state)
Transition from LOW-to-HIGH level
Don't Care (any input, including transitions)
, Q
, Q
HIGH Level (steady-state),
transition of the clock
The level of steady-state input at inputs A through H, respectively
B0
Gn
, Q
Package Description
The level of Q
H0
H
X
L
L
L
The level of Q
Inputs
X
X
L
L
L
A
or Q
A
, Q
G
H
H
X
X
L
L
X
, respectively, before the most recent
B
, or Q
January 1986
Revised February 2000
A...H
a...h
H
, respectively, before the
X
X
X
X
X
X
www.fairchildsemi.com
Q
Q
Q
Outputs
Internal
H
H
a
L
L
A0
A0
A
Q
Q
Q
Q
Q
Q
Q
b
B0
An
An
An
An
B0
B
Output
Q
Q
Q
Q
Q
Q
Q
h
Gn
Gn
Gn
Gn
H0
H0
H

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dm74als165 Summary of contents

Page 1

... DM74ALS165 8-Bit Parallel In/Serial Out Shift Register General Description The DM74ALS165 is an 8-bit serial register that, when clocked, shifts the data toward serial output, Q access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the SH/LD input. The DM74ALS165 also features a clock inhibit func- ...

Page 2

Logic Diagram Timing Diagram Typical Shift, Load, and Inhibit Sequences www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input ...

Page 4

Switching Characteristics over recommended free air temperature range. All typical values are measured at V Symbol Parameter Input f Maximum Frequency MAX t Propagation Delay Time PLH Load LOW-to-HIGH Level Output t Propagation Delay Time PHL Load HIGH-to-LOW Level Output ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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