dm74als1240a Fairchild Semiconductor, dm74als1240a Datasheet

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dm74als1240a

Manufacturer Part Number
dm74als1240a
Description
Octal 3-state Bus Driver
Manufacturer
Fairchild Semiconductor
Datasheet
© 2000 Fairchild Semiconductor Corporation
DM74ALS1240AWM
DM74ALS1240A
Octal 3-STATE Bus Driver
General Description
These octal 3-STATE bus drivers are designed to provide
the designer with flexibility in implementing a bus interface
with memory, microprocessor, or communication systems,
and
DM74ALS240A and DM74ALS241A. The output 3-STATE
gating control is organized into two separate groups of four
buffers. The DM74ALS1240A control inputs symmetrically
enable the respective outputs when set logic LOW. The 3-
STATE circuitry contains a feature that maintains the buffer
outputs in 3-STATE (high impedance state) during power
supply ramp-up or ramp-down. This eliminates bus glitch-
ing problems that arise during power-up and power-down.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
H
L
X
Z
Order Number
LOW Level Logic State
High Impedance (OFF) State
HIGH Level Logic State
Don't Care (Either LOW or HIGH Level Logic State)
are
low
G
H
L
L
power
Input
Package Number
dissipation
M20B
A
H
X
L
versions
Output
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Y
H
L
Z
DS006261
of
the
Features
Logic Diagram
Advanced oxide-isolated, ion-implanted Schottky TTL
process
Switching response specified into 500 and 50 pF load
Switching response specifications guaranteed over full
temperature and V
PNP input design reduces input loading
Low power dissipation version
Low level drive current: 74ALS
Package Description
CC
supply range
September 1986
Revised February 2000
16 mA
www.fairchildsemi.com

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dm74als1240a Summary of contents

Page 1

... DM74ALS240A and DM74ALS241A. The output 3-STATE gating control is organized into two separate groups of four buffers. The DM74ALS1240A control inputs symmetrically enable the respective outputs when set logic LOW. The 3- STATE circuitry contains a feature that maintains the buffer outputs in 3-STATE (high impedance state) during power supply ramp-up or ramp-down ...

Page 2

Absolute Maximum Ratings Supply Voltage Input Voltage Voltage Applied to Disabled Output Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage ...

Page 3

Switching Characteristics over recommended operating free air temperature range Symbol Parameter t Propagation Delay Time PLH LOW-to-HIGH Level Output t Propagation Delay Time PHL HIGH-to-LOW Level Output t Output Enable Time PZH to HIGH Level Output t Output Enable Time ...

Page 4

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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